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AWR1642: RTIA - RTIINTFLAG - INT0 not clearable

Christoph Saller
Intellectual 260 points
Part Number: AWR1642


Hi,

I am porting the FreeRTOS to the AWR1642. It is running quite well but I am having issues with timers. I think that the RTIA timer is blocking as the RTIINTFLAG - INT0 is never cleared.

I have this peace of code. It is executed in FIQ (CPS.M is 0x12):

        ; Clear interrupt flag
        MOVW    R0, #0xFC88
        MOVT    R0, #0xFFFF
        MOV     R1, #0x0F
        STR     R1, [R0]

0xFFFF_FC88 is the RTIINTFLAG regsiter. INT3 to INT1 are cleared (but those are not active, so I do not care about that). But INT0 always stays active. What is necessary to clear this bit?

Just for reference, this is used to setup the RTIA (here the  INt0 is cleared successfully)


static void prvSetupTimerInterrupt(void)
{
    /* Disable timer 0. */
    portRTI_GCTRL_REG &= 0xFFFFFFFEUL;

    /* Use the internal counter. */
    portRTI_TBCTRL_REG = 0x00000000U;

    /* COMPSEL0 will use the RTIFRC0 counter. */
    portRTI_COMPCTRL_REG = 0x00000000U;

    /* Initialise the counter and the prescale counter registers. */
    portRTI_CNT0_UC0_REG =  0x00000000U;
    portRTI_CNT0_FRC0_REG =  0x00000000U;

    /* Set Prescalar for RTI clock. */
    portRTI_CNT0_CPUC0_REG = 0x00000001U;
    portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
    portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;

    /* Clear interrupts. */
    portRTI_INTFLAG_REG =  0x0007000FU;
    portRTI_CLEARINTENA_REG = 0x00070F0FU;

    /* Enable the compare 0 interrupt. */
    portRTI_SETINTENA_REG = 0x00000001U;
    portRTI_GCTRL_REG |= 0x00000001U;
}
/*-----------------------------------------------------------*/

Register Definition:

/* Registers required to configure the RTI. */
#define portRTI_GCTRL_REG       ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
#define portRTI_TBCTRL_REG      ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
#define portRTI_COMPCTRL_REG    ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
#define portRTI_CNT0_FRC0_REG   ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
#define portRTI_CNT0_UC0_REG    ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
#define portRTI_CNT0_CPUC0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
#define portRTI_CNT0_COMP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
#define portRTI_CNT0_UDCP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
#define portRTI_SETINTENA_REG   ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
#define portRTI_INTFLAG_REG     ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )

  • 0
    TI__Guru 70100 points

    Hi Christoph,

    What I understood here that with the given code snippet you are able to clear the INT0 RTI to interrupt and with the OS internal function it doesn't clear, please confirm if my understanding is correct.

    And make sure that while clearing or enable/disable CPU is in privilege mode instead of user mode.

    Regards,

    Jitendra

  • 0 in reply to Jitendra Gupta
    Intellectual 260 points

    Hi Jitendra,

    no INT0 is not cleared. It stays 1 if I step through.

    However,  if make watch of the corresponding address and just monitor this without stepping/pausing, it is 0 most of the time. Is there some kind of delay? Or just a debugging issue?

    As I have written before, this is called in FIQ context with mode 0x12, what should be priviliged. Please correct me if I am mistaken here

  • 0 in reply to Christoph Saller
    TI__Guru 70100 points

    Hello Christoph,

    Could you confirm that without a debugger connection, the application code is able to get and clear the INT0 interrupt? As per your original thread, are you not able to clear the interrupt only with assembly code but works well with C code? Am I correct here with my assumption?

    Because the same RTI interrupt is being used by RTOS (RIT-A on MSS) which is used by mmWave SDK applications.

    Regards,

    Jitendra

  • 0 in reply to Jitendra Gupta
    Intellectual 260 points

    Hi Jitendra,

    no, has nothing to do with asm or C or debugger connected. It is like this:

    1) stepping through the ISR code, the Interrupt is not cleared in the register view after  this code snippet

        ; Clear interrupt flag
            MOVW    R0, #0xFC88
            MOVT    R0, #0xFFFF
            MOV     R1, #0x0F
            STR     R1, [R0]

    2) If I monitor the interrupt pending register it is cleared sometimes (as this happens very fast I cannot say if it every time or not)

    My code seems to run fine, but this behavior bothers me a bit.

  • 0 in reply to Christoph Saller
    TI__Guru 70100 points

    Hi Christoph,

    Best way to check from the code based counter to verify if the register bit is getting cleared.

    Regards,

    Jitendra

  • 0 in reply to Jitendra Gupta
    Intellectual 260 points

    Could you elaborate? What is a "code base counter" ?

  • 0 in reply to Christoph Saller
    TI__Guru 70100 points

    I was suggesting don't use the JTAG connection or do the debugging. But check the register status using application code and throw an error it doesn't see register status as expected. You need to execute this application from flash as mmw demo can run on the device.

    Regards,

    Jitendra