Other Parts Discussed in Thread: MMWAVE-DFP
Tool/software: Code Composer Studio
Hi sir,
I would like to port lab sample code ''lab0012_srr_16xx" to IWR6843ISK.
But I have an error message "Error: MMWDemoMSS mmWave open configuration failed [Error code -3129]"
Please help to solve this problem
CCS 9.3
SDK 3.3.0.3
BIOS : 6.73.1.01
openCfg.freqLimitLow = 0U;
openCfg.freqLimitHigh = 0U;
openCfg.defaultAsyncEventHandler = MMWave_DefaultAsyncEventHandler_MSS;
openCfg.chCfg.rxChannelEn = RX_CHANNEL_1_2_3_4_ENABLE;
openCfg.chCfg.txChannelEn = TX_CHANNEL_1_2_3_ENABLE;
openCfg.chCfg.cascading = 0;
openCfg.lowPowerMode.lpAdcMode = LP_ADC_MODE_LOW_POWER;
openCfg.adcOutCfg.fmt.b2AdcBits = ADC_BITS_16;
openCfg.adcOutCfg.fmt.b2AdcOutFmt = ADC_FORMAT_COMPLEX;
openCfg.adcOutCfg.fmt.b8FullScaleReducFctr = 0;
#define SUBFRAME_CONF_SRR /* One subframe SRR80. */
/*! @brief SRR profile ID. */
#define PROFILE_SRR_PROFILE_ID (0U)
/*! @brief HPF 1 corner frequency. */
#define PROFILE_SRR_HPFCORNER_FREQ1_VAL RL_RX_HPF1_175_KHz
/*! @brief HPF 2 corner frequency. */
#define PROFILE_SRR_HPFCORNER_FREQ2_VAL RL_RX_HPF2_350_KHz
/*! @brief Rx gain is kept at the maximum . */
#define PROFILE_SRR_RX_GAIN_VAL (44U)
/*! @brief ADC Output rate is 5Mhz. */
#define PROFILE_SRR_DIGOUT_SAMPLERATE_VAL (5000U)
#define PROFILE_SRR_ADC_SAMPLE_VAL (256U)
#define PROFILE_SRR_IDLE_TIME_VAL (300U)
#define PROFILE_SRR_RAMP_END_TIME_VAL (5600U)
#define PROFILE_SRR_START_FREQ_GHZ (60.5f)
#define PROFILE_SRR_START_FREQ_VAL (CONV_FREQ_GHZ_TO_CODEWORD(PROFILE_SRR_START_FREQ_GHZ))
#define PROFILE_SRR_TXOUT_POWER_BACKOFF (0U)
#define PROFILE_SRR_TXPHASESHIFTER_VAL (0U)
#define PROFILE_SRR_FREQ_SLOPE_MHZ_PER_US (8.0f)
#define PROFILE_SRR_FREQ_SLOPE_VAL (CONV_SLOPE_MHZ_PER_US_TO_CODEWORD(PROFILE_SRR_FREQ_SLOPE_MHZ_PER_US))
#define PROFILE_SRR_TX_START_TIME_VAL (100U) // 1us
#define PROFILE_SRR_ADC_START_TIME_VAL (480U) // 4.8us
#define PROFILE_SRR_LAMBDA_MILLIMETER (MMWDEMO_SPEED_OF_LIGHT_IN_METERS_PER_USEC/PROFILE_SRR_START_FREQ_GHZ)
/*! @brief Define 128 chirps, the first 64 will have an idle time of
* 3us, and the remaining 64 will have an idle time of 14.8us
* (11.8us extra 'idle time') */
#define CHIRP_SRR_0_PROFILE_ID (0U)
#define CHIRP_SRR_0_START_INDEX (0U)
#define CHIRP_SRR_0_END_INDEX (63U)
#define CHIRP_SRR_0_START_FREQ_VAL (0U)
#define CHIRP_SRR_0_FREQ_SLOPE_VAL (0U)
#define CHIRP_SRR_0_IDLE_TIME_VAL (0U)
#define CHIRP_SRR_0_ADC_START_TIME_VAL (0U)
#define CHIRP_SRR_0_TX_CHANNEL (TX_CHANNEL_1_ENABLE)
#define CHIRP_SRR_1_PROFILE_ID (0U)
#define CHIRP_SRR_1_START_INDEX (64U)
#define CHIRP_SRR_1_END_INDEX (127U)
#define CHIRP_SRR_1_START_FREQ_VAL (0U)
#define CHIRP_SRR_1_FREQ_SLOPE_VAL (0U)
#define CHIRP_SRR_1_IDLE_TIME_VAL (1180U)
#define CHIRP_SRR_1_ADC_START_TIME_VAL (0U)
#define CHIRP_SRR_1_TX_CHANNEL (TX_CHANNEL_1_ENABLE)
/*! @brief SUBFRAME configuration. */
#define SUBFRAME_SRR_CHIRP_START_IDX (0U)
#define SUBFRAME_SRR_CHIRP_END_IDX (127U)
#define SUBFRAME_SRR_LOOP_COUNT (1U)
#define SUBFRAME_SRR_PERIODICITY_VAL (6000000U) // 30ms
#define SUBFRAME_SRR_TRIGGER_DELAY_VAL (0U)
#define SUBFRAME_SRR_NUM_REAL_ADC_SAMPLES (PROFILE_SRR_ADC_SAMPLE_VAL * 2)
#define SUBFRAME_SRR_NUM_CMPLX_ADC_SAMPLES (PROFILE_SRR_ADC_SAMPLE_VAL)
#define SUBFRAME_SRR_CHIRPTYPE_0_NUM_CHIRPS ((CHIRP_SRR_0_END_INDEX - CHIRP_SRR_0_START_INDEX + 1)*SUBFRAME_SRR_LOOP_COUNT)
#define SUBFRAME_SRR_CHIRPTYPE_1_NUM_CHIRPS ((CHIRP_SRR_1_END_INDEX - CHIRP_SRR_1_START_INDEX + 1)*SUBFRAME_SRR_LOOP_COUNT)
#define SUBFRAME_SRR_NUM_TX (1U) //Two Tx simultaneous
#define SUBFRAME_SRR_NUM_VIRT_ANT (SUBFRAME_SRR_NUM_TX*NUM_RX_CHANNELS)
#define SUBFRAME_SRR_NUM_ANGLE_BINS (32U)
#define SUBFRAME_SRR_NUM_CHIRPS_TOTAL ((SUBFRAME_SRR_CHIRP_END_IDX - SUBFRAME_SRR_CHIRP_START_IDX + 1) * SUBFRAME_SRR_LOOP_COUNT)
#define PROFILE_SRR_RANGE_RESOLUTION_METERS ((MMWDEMO_SPEED_OF_LIGHT_IN_METERS_PER_USEC * PROFILE_SRR_DIGOUT_SAMPLERATE_VAL)/ (2000.0f * PROFILE_SRR_FREQ_SLOPE_MHZ_PER_US * SUBFRAME_SRR_NUM_CMPLX_ADC_SAMPLES) )
#define SUBFRAME_SRR_CHIRPTYPE_0_CHIRP_REPETITION_PERIOD_US ((CHIRP_SRR_0_IDLE_TIME_VAL + PROFILE_SRR_IDLE_TIME_VAL + PROFILE_SRR_RAMP_END_TIME_VAL)/100.0f)
#define SUBFRAME_SRR_CHIRPTYPE_0_VEL_RESOLUTION_M_P_S (((1000.0f/SUBFRAME_SRR_CHIRPTYPE_0_CHIRP_REPETITION_PERIOD_US)/SUBFRAME_SRR_CHIRPTYPE_0_NUM_CHIRPS)*(PROFILE_SRR_LAMBDA_MILLIMETER/2))
#define SUBFRAME_SRR_CHIRPTYPE_0_MAX_VEL_M_P_S (SUBFRAME_SRR_CHIRPTYPE_0_VEL_RESOLUTION_M_P_S*SUBFRAME_SRR_CHIRPTYPE_0_NUM_CHIRPS/2)
#define INV_SUBFRAME_SRR_CHIRPTYPE_0_VEL_RESOLUTION_M_P_S (1.0f/SUBFRAME_SRR_CHIRPTYPE_0_VEL_RESOLUTION_M_P_S)
#define SUBFRAME_SRR_CHIRPTYPE_1_CHIRP_REPETITION_PERIOD_US ((CHIRP_SRR_1_IDLE_TIME_VAL + PROFILE_SRR_IDLE_TIME_VAL + PROFILE_SRR_RAMP_END_TIME_VAL)/100.0f)
#define SUBFRAME_SRR_CHIRPTYPE_1_VEL_RESOLUTION_M_P_S (((1000.0f/SUBFRAME_SRR_CHIRPTYPE_1_CHIRP_REPETITION_PERIOD_US)/SUBFRAME_SRR_CHIRPTYPE_1_NUM_CHIRPS)*(PROFILE_SRR_LAMBDA_MILLIMETER/2))
#define SUBFRAME_SRR_CHIRPTYPE_1_MAX_VEL_M_P_S ((SUBFRAME_SRR_CHIRPTYPE_1_VEL_RESOLUTION_M_P_S*SUBFRAME_SRR_CHIRPTYPE_1_NUM_CHIRPS/2)
#define INV_SUBFRAME_SRR_CHIRPTYPE_1_VEL_RESOLUTION_M_P_S (1.0f/SUBFRAME_SRR_CHIRPTYPE_1_VEL_RESOLUTION_M_P_S)
#define SUBFRAME_SRR_MIN_SNR_dB (14.0f)
#define SUBFRAME_SRR_NUM_CHIRPTYPES (2U)
BR
Thanks
Frank
