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LDC0851: Can the LDC0851 used in stacked coil configuration with odd-numbered layers?

af36
Prodigy 250 points
Part Number: LDC0851

All stacked layout examples I see use either 2, 4, or 8 layers. Does there need to be an even number of layers for the LSENSE and LREF coils, or would 3/3 work in a 6 layer configuration?

Additionally, it appears the Spiral_Inductor_Designer tab of the LDC_Tools-ext49.xlsx (from slyc137e) calculates inductance assuming non-stacked configuration whereas the web version of the Coil Designer assumes stacked based on the CAD output. Can you confirm?

In my application, I have an outer diameter of 330 mils and cannot fit more than 4 turns per layer. I need to know how many layers I need to keep the inductance above the LDC0851 minimum (1.8 uH) with a metal target only 0.1 mm away (essentially a touch application). It seems it may not be possible without a 12 or more layer board based on the Excel worksheet with 4 mil traces... unless I can add a small series inductor similar to this post: https://e2e.ti.com/blogs_/b/analogwire/archive/2014/06/10/inductive-sensing-how-to-use-a-tiny-2mm-pcb-inductor-as-a-sensor

Is that an option using the LDC0851, and are there any other suggestions related to its implementation? Any thoughts on feasibility would be much appreciated.

  • 0
    TI__Expert 3435 points

    Hi,

    Thank you for contacting us. Please find the answers below.

    1. It is only possible to have even number layers as the layout with odd numbers is not possible. 

    2. Both the excel calculator and the web version can only do non-stacked configurations. 

    3. Is there any reason for limiting the turns per layer 4 only? We recommend increasing the turns to at least 10 to limit the number of layers. unfortunately, the series inductor would not help with LDC0851 devices as the inductance between LSENSE and LREF should be tightly matched(within 1%). No surface mount inductors can achieve this tolerance. 

    Regards

    Sharath.

  • 0 in reply to Sharath Vallamkonda
    Prodigy 250 points

    Hi Sharath,

    My application has an conductive (stainless steel) target that passes through a hole in the PCB. On the top side of the PCB, the conductive target widens such that it contacts the PCB (with a layer of kapton insulator in between).

    The hole diameter is 236.2 mil. The outer diameter of the conductive target on the top side of the PCB is 330 mil. The distance between adjacent conductive targets, which are intended to be used in the same hole/sense fashion, is approximately 24 mil. I already know I will need to alternate excitation frequencies to avoid cross-talk between adjacent LDC0851's. Using the 330 mil and 236.2 mil values, as well as an assumption that I will need 26 mil spacing for an 18 mil via pad with 4 mil clearance, I used the calculators to determine that I had to keep turns per layer to 4. I can increase the number of layers accordingly to meet the minimum inductance requirement, unless you have any other ideas.

    Below is a crude example of the application I am talking about. The conductive SS targets are the blue cylinders passing through a green PCB.

    Thanks,

    Aaron

  • 0 in reply to af36
    TI__Expert 3435 points

    Hi Aaron,

    It is recommended that the adjacent targets are at least 20% of the coil diameter away from the edge of each coil. Otherwise, adjacent targets could interact with the wrong sensor coil.

    If possible, you can try reducing the true spacing between the traces which will increase the inductance and you might be able to fit more turns per layer. If all these options are exhausted, then the number of layers can be increased as per the excel tool.

    Regards

    Sharath.