Other Parts Discussed in Thread: AWR1642
Hi,
I have a few basic questions.
1- I understand that that the Minimum value value for ADC sampling rate is 2Msps or 2000 ksps.
For AWR1642BOOST, maximum ADC sampling rate for 1x COMPLEX mode is (0.9x6.25=5.625 MHz) or it is 5625 ksps.
For AWR1642BOOST, maximum ADC sampling rate for REAL and 2x COMPLEX mode is ( (0.9x6.25)/2= 2.8125 MHz) or it is 28125.5 ksps.
Please confirm is my above understanding correct, both in terms of sampling frequency and in terms of ksps ?
2- As an example, please refer the user guide for mmwave sdk 2.0.0.4 (document number Product Release 2.0.0 , Release date 26 April, 2018, Document version 1.0 ) , page 16, 17. Please also refer user guide for mmwave sdk 3.3.0.3 (document number Product Release 3.3 , Release date 17 Sept, 2019, Document version 1.0 ) , page 21.
The following formula is given : (<numAdcSamples> / <digOutSampleRate> = "ADC Sampling Time")
My question are :
3- Although the user guide for mmwave sdk 3.3.0.3 states that value of less than 64 has not been validated for number of ADC samples, however, is there any theoretical and / or practical MINIMUM and MAXIMUM limits for number of ADC samples. Please refer a relevant TI document as well. In fact, I am more interested in MINIMUM number of ADC samples allowed / permissible.
4- The Ramp Timing Calculator in mmwave Studio shows 90 % Settling, 95% Settling, 99 % Settling. Can you please elaborate what exactly is meant by this ?
Thanks and best regards