Hi Experts,
Could you let me know about ESMSR1 to 7 register bits description.
I believe that MSS can check the status by using the bit when a watch dog error occurs in DSS.
Thank you and best regards,
Hitoshi
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Hi Experts,
Could you let me know about ESMSR1 to 7 register bits description.
I believe that MSS can check the status by using the bit when a watch dog error occurs in DSS.
Thank you and best regards,
Hitoshi
Hi Hitoshi,
Please refer to TRM @http://www.ti.com/cn/lit/ug/swru522d/swru522d.pdf.
Let me know if you find anything missing.
Yogesh
Hi Yogesh,
Thanks, I was able to find the table "Table 1-13. MSS_ESM Mapping” on page 196.
The number of the table describes the bit of ESMSRx registers I believe.
I still can not understand the mapping for the bit in ESMSRx.
28.2.2 Module Operation in page 3285
The error status registers ESMSR1, ESMSR4, ESMSR2, ESMSR3 provide status information on a pending error of Group1 (Channel 0-31), Group1(Channel 32-63), Group1 (Channel 64-95), Group2, and Group3,
ESMSR1, MSS_ESM Group 1 ( Channel 0 to 31 )
ESMSR4, MSS_ESM Group 1 ( Channel 32 to 63 )
ESMSR7, (?) MSS_ESM Group 1 ( Channel 64 to 95 ) ( can not see 64 to 95?)
ESMSR2, MSS_ESM Group 2
ESMSR3 MSS_ESM Group 3
How about DSS_ESM group 1 to 3?
Could you please let me know correct mapping the group to ESMSR1,2,3,4 and 7?
Best regards,
Hitoshi Sugawara
Hi Yogesh,
I have found the same post.
https://e2e.ti.com/support/sensors/f/1023/t/711771
If ESMSR register setting for IWR1843 is different from this, please let me know.
Thank you and best regards,
Hitoshi