This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MMWCAS-RF-EVM: MSS ESM Fault for AWR1243P

Part Number: MMWCAS-RF-EVM
Other Parts Discussed in Thread: MMWCAS-DSP-EVM,

Hi, we are developping our own cascade RF board with 4 AWR1243P. We have run everything good with MMWCAS-RF-EVM and MMWCAS-DSP-EVM.

Then We try to run the master AWR1243P on our own RF board with MMWCAS-DSP-EVM. We modify the Cascade_Configuration_TestSource.lua to set only the master chip and the script run successfully. Then we start the Cascade_Capture.lua which is nothing modified. After starting the Framing_Control of the master chip, it reports: "[DeviceId-0] MSS ESM Fault error status Async event received(0x400000, 0x0)".

The test is using mmWaveStudio 2.1.0.0. The firmware is xwr12xx_metaImage.bin in mmwave_dfp_01_02_05_01 and  is downloaded successfully by Cascade_Configuration_TestSource.lua. The AWR1243P status is XWR1243/ASIL-B/SOP:4/ES:3.

What is the problem? We only weld 1 chip for testing. Will it cause the problem?

  • Hi,

    If I understand correctly you have a custom 4 chip cascade board. Right now you have only the master chip soldered on the board.

    Is you board identical to the TI cascade board?

    Thank you

    Cesar

  • Yes, it is designed following the TI cascade board. Should I change the working mode as single, but not master to work alone for this master chip?

  • Hi Daning, 

    Are you capturing data with your own custom host processors board, or with mmWave Studio and the MMWCAS-DSP-EVM still? 

    Thank you,

    -Randy

  • Hi Randy, we are using MMWCAS-DSP-EVM to capture the data.

  • Hi Daning,

    The ESM fault indicates frame clock failure. Please note that in cascade mode, you need to have DIG_SYNCOUT of master routed on PCB and connected to both slave and back to Master DIG_SYNCIN. This DIG_SYNCIN triggers the frame clock and if this is not done or has jitter, you could see the failure.

    Please check your connection. Also try running in SINGLE_CHIP mode and see if problem is resolved. 

    Regards,

    Kaushal

  • Hi Kaushal, thanks for your reply. How to set the SINGLE_CHIP mode? I cannot find the sample of the LUA script in the mmwave_studio. Could you provide me a sample script to set the SINGLE_CHIP mode with MMWCAS-DSP-EVM?

    Best regards!

    / Daning

  • Hi Daning, 

    In the case of our mmWave Studio lua example scripts, single-chip vs. cascade master/save mode are selected using the ar1.ChanNAdcConfig_mult() function. Please see the output from the mmWave Studio Lua Shell help function. The last argument defines the device mode. 

    >help ar1.ChanNAdcConfig_mult
    Int32 ar1.ChanNAdcConfig_mult(UInt16 RadarDeviceId, UInt16 Tx0En, UInt16 Tx1En, UInt16 Tx2En, UInt16 Rx0En, UInt16 Rx1En, UInt16 Rx2En, UInt32 Rx3En, Int32 BitsVal, UInt32 FmtVal, UInt32 IQSwap, UInt16 CasCadeMode) - Static device config API which defines configure both the Transmiter and Reciever channels of Radar device and also ADC data format output
    _I_ UInt16 RadarDeviceId - Radar Device Id
    _I_ UInt16 Tx0En - Tx0 channel
    _I_ UInt16 Tx1En - Tx1 channel
    _I_ UInt16 Tx2En - Tx2 channel
    _I_ UInt16 Rx0En - Rx0 channel
    _I_ UInt16 Rx1En - Rx1 channnel
    _I_ UInt16 Rx2En - Rx2 channel
    _I_ UInt32 Rx3En - Rx3 channel[b15:0] + (CascadePinOutCfg[b31:16] b16:ClkOutMasterDis, b17:SynOutMasterDis, b18:ClkOutSlaveEna, b19:SynOutSlaveEna, b20:IntLOMasterEna, b21:OSCClkOutMasterDis, b22:INTFRCMasterEna)
    _I_ Int32 BitsVal - Number of ADC bits
    _I_ UInt32 FmtVal - ADC output format[b15:0] + FullScaleReductionFactor[b31:16]
    _I_ UInt32 IQSwap - ADC Mode
    _I_ UInt16 CasCadeMode - CascadeMode(Single Chip: 0x0000, MultiChip Master:0x0001, MultiChip Slave:0x0002)

  • Hi Randy,

    Thanks for your information!

    Best regards!

    / Daning