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AWR1843: LVDS output and stackup = 8 layers

Long Ta1
Prodigy 100 points
Part Number: AWR1843

Hi Vivek,

1- We operate Clk = 300 MHz in DDR mode. We have a "C" shape routing path instead of a straight one. Could you let me know the maximum allowable skews/delays for length matchings? I believe the 5 mils and 5 mils on the EVM is for 900 MHz DDR?

I'd keep the 5 mils between P&N lines, but would like to know your feedback on our LVDS length matching needs.

2- We increased the board stackup from 6 to 8 layers, 2 more plane layers for better routing & thermal management - would you have any concerns?

Kind regards,

Long

  • 0
    TI__Guru 58035 points

    Hello Long,

    1) The allowable skew allowed between the LVDS lanes will actually depend on how much tolerance your LVDS receiver has. But 50-60 mils mismatch between the lanes should not cause an issue. Between the differential pair maintain within 5mil tolerance.

    2) Moving to 8 layers is not an issue. Just ensure the RF layer thickness and dielectric are not changed.

    Regards,

    Vivek