Hi expert,
In the 4-chip cascade radar demo we see the pix clock edge polarity setting are different for the VIP VIN3A port. Could you please give some details about why we need to use rising edge for this single port as below?
Thank you.
if (pInstPrm->vipInstId == VPS_CAPT_VIP_MAKE_INST_ID(VPS_VIP2, VPS_VIP_S0, VPS_VIP_PORTA))
{
pPortCfg->comCfg.pixClkEdgePol = SYSTEM_EDGE_POL_RISING;
}
else
{
pPortCfg->comCfg.pixClkEdgePol = SYSTEM_EDGE_POL_FALLING;
Bsp_platformSetVipClkInversion(pInstPrm->vipInstId, TRUE);
}
Regards,
Allen
