IWR6843: Large SPI Transfer Issues

Hello,
I am having some difficulty getting the SPI device on the IWR6843 to transfer large frames.
Specifically, if I try to send more than 128[bytes] (i.e. increase PX_SPI_BLK_SIZE) in a single transfer no data is shifted out on MOSI and the clock does not cycle. SPI_transfer does not report an error.
I have enabled SPI_MULT_ICOUNT_SUPPORT in mibspi_dma.c, but it does not seem to make a difference.
I feel like I must be missing something obvious, or that I have a fundamental misunderstanding of the SPI peripheral.
I have attached the relevant code.

SPI instance setup:

/* Setup the data stream SPI Parameters */
SPI_Params_init(&spiParams);
spiParams.transferMode = SPI_MODE_BLOCKING;
spiParams.frameFormat = SPI_POL1_PHA0;        // MODE 2
spiParams.shiftFormat = SPI_MSB_FIRST;
spiParams.dmaHandle = gMmwMssMCB.dmaHandle;
spiParams.dmaEnable = 1U;
spiParams.eccEnable = 1U;
spiParams.pinMode = SPI_PINMODE_4PIN_CS;
spiParams.mode = SPI_MASTER;
spiParams.dataSize = 16U;                     // 16 bits per transfer; with SPI_MULT_ICOUNT_SUPPORT defined, should enable upto 1024[bit] transfers

spiParams.u.masterParams.numSlaves = 1U;
spiParams.u.masterParams.bitRate = gMmwMssMCB.cfg.platformCfg.spiClockRate;
spiParams.u.masterParams.c2tDelay = 0U;       // Chip select active to transmit start delay
spiParams.u.masterParams.t2cDelay = 0U;       // Transmit end to chip select inactive delay
spiParams.u.masterParams.wDelay = 0U;         // Intra-transmission delay

spiParams.u.masterParams.slaveProf[0].chipSelect = 0U;
spiParams.u.masterParams.slaveProf[0].dmaCfg.txDmaChanNum = 1U;
spiParams.u.masterParams.slaveProf[0].dmaCfg.rxDmaChanNum = 0U;
spiParams.u.masterParams.slaveProf[0].ramBufLen = MIBSPI_RAM_MAX_ELEM;

/* Open the data stream SPI instance */
gMmwMssMCB.spiStreamHandle = SPI_open(0, &spiParams);
if (gMmwMssMCB.spiStreamHandle == NULL)
{
    System_printf("%s::%d Error: MMWDemoMSS Unable to open the data stream SPI Instance\n", __FILE__, __LINE__);
    MmwDemo_debugAssert (0);
    return;
}

SPI transfer code:

#if !defined(PX_SPI_BLK_SIZE)
#define PX_SPI_BLK_SIZE 128
#endif

static int32_t spi_write(struct px_spi_context* context, struct px_spi_msg *spi_msg)
{
    uint8_t term[] = {0x11, 0x22, 0x33, 0x44};
    SPI_Transaction spi_transaction;
    SPI_Handle spi_fd;
    uint8_t *dataPt;
    uint32_t cs_fd;
    int32_t retval;
    size_t size;

    assert(context != NULL);
    assert(spi_msg != NULL);

    spi_fd = context->config.spi_fd;
    cs_fd = context->config.cs_fd;
 
    spi_msg->header.index = context->msg_index++;

    /* Assert CS line */
    GPIO_write(cs_fd, 0U);

    spi_transaction.rxBuf = NULL;
    spi_transaction.slaveIndex = 0;

    dataPt = (uint8_t *)spi_msg;
    size = sizeof(*spi_msg);

    while (size > 0) {
        spi_transaction.count = size > PX_SPI_BLK_SIZE ? PX_SPI_BLK_SIZE : size;
        spi_transaction.txBuf = dataPt;
        retval = SPI_transfer(spi_fd, &spi_transaction);
        if (retval == 0) {
            goto PX_SPI_WRITE_ERR;
        }

        dataPt += PX_SPI_BLK_SIZE;
        size -= PX_SPI_BLK_SIZE;
    }

    spi_transaction.count = 4;
    spi_transaction.txBuf = term;
    retval = SPI_transfer(spi_fd, &spi_transaction);
    if (retval == 0) {
        goto PX_SPI_WRITE_ERR;
    }

    /* Deassert CS line */
    GPIO_write(cs_fd, 1U);

    return PX_SPI_ERROR__NONE;

PX_SPI_WRITE_ERR:
    GPIO_write(cs_fd, 1U);
    return retval;
}