CCS/AWR1243: AWR requires a delay between consequtive SPI CS

Timur Suanov

Part Number: AWR1243
Other Parts Discussed in Thread: TDA2

Tool/software: Code Composer Studio

Hi, Experts!

There is a requirement "There should be a delay at least 2 SPI clocks between consecutive CS in Radar Interface Control document (p.17, revision 0.97)". Could you suggest how can it be implemented with TDA2?

Thank you

Timur.

over 5 years ago

0 Stanley Liu over 5 years ago

TI__Guru 50045 points

McSPI on TDA2 has CS timing control. It is configured via MCSPI_CHxCONF.TCS0.

Please refer to TDA2 Technical Reference Manual, Chapter 24.3.4.3.7 Chip-Select Timing Control.

0 Alex Belyaev over 5 years ago in reply to Stanley Liu

Intellectual 272 points

Hi, Stanley.

I've seen this. But the thing is a delay between two consecutive SPI CS, not a delay between CS edge and SPI CLCK.

Thanks,

Timur.

0 Stanley Liu over 5 years ago in reply to Alex Belyaev

TI__Guru 50045 points

That timing requirement is met by TDA2 McSPI as long as the CS Force mode is not used.

Please refer to 24.3.4.3.5.2 Force SPIEN[x] Mode.

0 Timur Suanov over 5 years ago in reply to Stanley Liu

Intellectual 290 points

We do not use CS Force mode. There is a clear delay between two consecutive SPI CS (seen with oscillograph), but it is too short if SPI frequency is 6 MHz or lower. Mentioned timing requirement could be met by setting SPI frequency 12 or 24 MHz (as the SPI clocks grow shorter).

So the duration of that delay is hardware-given or can be software-specified?

Thank you,

Timur.

0 Stanley Liu over 5 years ago in reply to Timur Suanov

TI__Guru 50045 points

In our reference SW implementation in Radar SDK, the 8Mhz and 24Mhz have been validated.

0 Timur Suanov over 5 years ago in reply to Stanley Liu

Intellectual 290 points

Thank you, Stanley.

Regards,

Timur

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CCS/AWR1243: AWR requires a delay between consequtive SPI CS