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AWR2243: AWR2243: PMIC_CLKOUT, SYNC_OUT, TDO

Tomotaroh Kohro
Genius 14695 points
Part Number: AWR2243

Hello support team.

Data Manual mentioned the below:

The SOP pins are driven externally (weak drive) and the AWR device senses the state of these pins during bootup to decide the bootup mode. After boot the same pins have other functionality.

 

There is no description in the Data Manual regarding the timing of how long after the reset is released the output of the above 3 pins.

Please clarify when these three pins are changed output after releasing reset.

Customer would like to know if these pins are changed to output by fixed timing or if these pins are changed to output by setting the internal register.

 

Br

KORO

  • 0
    TI__Guru*** 141404 points

    Hi,

    Our hw team will review this question and will get back to you

    thank you
    Cesar

  • 0
    TI__Mastermind 26985 points

    Hello Koro,

    The SOP state will be latched NRESET reaches around half of the voltage of VIO (at 1.7V for 3.3V IO). Once the SOP state has been latched the SOP pins can be configured for another purpose. 

    However, it is important to take care that if the device happens go into reset unexpectedly (i.e. a power fault causes the PMIC to toggle the NRESET pin) the SOP pins will be in their correct state when this occurs.

    Regards,

    Adrian

  • 0 in reply to aozer
    TI__Genius 14695 points

    Hello Adrian-san

    Thanks a lot.

    I saw the DM of AWR2243(awr2243.pdf).

    This DM has "5.9.1 Power Supply Sequencing and Reset Timing".

    From this figure, "SOP Hold time to nRESET" is taken some time from "DC power Stable before nRESET release".

    Then I would like to ask.

    You mentioned "nRESET reaches around half of the voltage of VIO (at 1.7V for 3.3V IO).".

    I would like to know this VIO meaning.

    Br

    KORO

  • 0 in reply to Tomotaroh Kohro
    TI__Mastermind 26985 points

    Hello Koro,

    VIO is the IO voltage, it is the voltage supplied on pin R13 that provides power to all of the CMOS I/Os. So, if you have an IO voltage of 3.3V the NRESET will latch the SOP state when it reaches around half of the I/O voltage (1.7V) after the NRESET is released and begins to pull up to 3.3V. After this the SOP pins can be configured for another purpose.

    Regards,

    Adrian

  • 0 in reply to aozer
    TI__Genius 14695 points

    Hello Adrian-san

    Thanks a lot.

    I see.

    From previous explanation, these pin can be used for customer when system will be started.

    Br

    KORO