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MMWCAS-RF-EVM: the first frame captured in mmwave studio is wrong

Chris Meng
Mastermind 36665 points
Part Number: MMWCAS-RF-EVM
Other Parts Discussed in Thread: TDA2, , MMWCAS-DSP-EVM

Hi,

My customer found when they use TI cascaded EVM to capture ADC raw data, the first frame data is wrong, but the later frames are ok. Why this happed? Is it due to the VIP IO delay setting? If it is true, why the later frame will be correct? Would you pls help to point out me the related code in vision sdk?

Below is the first issue frame info.

  • 0
    TI__Mastermind 36665 points

    Hi,

    My customer made own RF board. They used adapter board to connect their RF board to our DSP processor board. Do they need to do the VIP IO delay adjustment on processor sdk? if yes, would you pls kindly how?

  • 0 in reply to Chris Meng
    TI__Guru*** 141404 points

    Chris,

    Can you please clarify if the customer is implementing it's own demo on the TDA or if it is capturing raw data using the imaging kit?

    Since processor sdk is mentioned my understanding it that the customer is implementing it's own demo.

    thank you

    Cesar

  • 0 in reply to Cesar
    TI__Mastermind 36665 points

    Cesar，

    Customer is using mmWave studio to capture the RAW data on TI cascaded RF board and also their own RF board.

    As far as I know, the image we burned on TDA2 for mmWave studio is based on processor vision sdk (Linux).

  • 0 in reply to Chris Meng
    TI__Guru*** 141404 points

    Hi Chris,

    We need to understand if this issue is reproduced out of the box with the TI imaging kit.

    I will check with the team and get back to you

    thank you

    Cesar

  • 0 in reply to Cesar
    TI__Mastermind 36665 points

    Cesar,

    It seems a known issue. You can find below in mmwave_studio_cascade_user_guide.pdf. Why it happens? Why it happens only on the first captured frame and later frames are ok?

     

  • 0 in reply to Chris Meng
    TI__Genius 17820 points

    Hi Chris, 

    Thank you for including the system stack block diagrams. A few more debug options/questons.

    • This still looks like a data/signal integrity issue to me
    • Do they have a MMWCAS-RF-EVM they can test against?
    • What are the losses of CSI2 channels from the MMWCAS-DSP-EVM to the custom RF board? Including a second adapter board may introduce loss, mismatch and additional that may cause a CSI2 signal integrity issue at the MMWCAS-DSP-EVM FPGA CSI2 bridges
      • Can they check CSI2 signal integrity by probing CSI2 clock and data vias near the FPGA CSI2 bridge RX pins
    • Device to device mismatch may also require further buffer synchronization on the MMWCAS-DSP-EVM processors SDK demos
      • All AWR CSI2 transmit channels on our MMWCAS-RF-EVM care length matched to each other so delay skew into the VIP ports of the TDA2 is kept small
    • How well is frame synchronization delay matched on their custom RF board? 
    • How well is LO network delay matched on their custom RF board?

    Thanks,

    -Randy

  • 0 in reply to Randy Rosales
    TI__Genius 17820 points

    Hi Chris, 

    Thank you for the additional info over e-mail. Looks like the target generator is functional and providing good data. I think that probably rules out a fundamental signal integrity issue. 

    Can you still please check: 

    • Device to device mismatch may also require further buffer synchronization on the MMWCAS-DSP-EVM processors SDK demos
      • All AWR CSI2 transmit channels on our MMWCAS-RF-EVM care length matched to each other so delay skew into the VIP ports of the TDA2 is kept small
    • How well is frame synchronization delay matched on their custom RF board? 
    • How well is LO network delay matched on their custom RF board?

    Thank you,

    -Randy