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AWR2243: Question on LO/digital sync/40Mhz clock routing in 4-chip cascaded system

Chris Meng
Mastermind 37726 points
Part Number: AWR2243
Other Parts Discussed in Thread: TDA2

Hi,

We have checked SWRA574B AWR2243 Cascade and have some questions about routing length. Would you pls help?

1. Must the LO routing length be exactly same?

2. For Digital Frame Sync, as there is already some inter chip imbalance on different chip, I think the length may not vneed to exactly same. Then what's the tolerance of the length difference for Digital Frame Sync?

3. For 40Mhz clock, as there is no phase/delay matching requirements on this clock, the routing length for different chip can be different, right?

  • 0
    TI__Guru*** 148514 points

    Hi,

    The cascade team will review this question and reply by tomorrow

    thank you

    Cesar

  • 0 in reply to Cesar
    TI__Mastermind 18500 points

    Hi Chris, 

    1. Must the LO routing length be exactly same?

    For best phase match, yes, it is recommended to route LO to within minimum delay match which can be fabricated. Phase mismatch will reduce VCO phase correlation factor and increase phase noise across cascaded devices. This increased phase noise will impact short-range/bumper performance. 

    2. For Digital Frame Sync, as there is already some inter chip imbalance on different chip, I think the length may not vneed to exactly same. Then what's the tolerance of the length difference for Digital Frame Sync?

    The tolerance of the frame sync is the tolerance of the ADC sample window and subsequent CSI-2 data transfer alignment. Increased mismatch will skew the ADC sample windows and skew the CSI-2 transfer times. 

    3. For 40Mhz clock, as there is no phase/delay matching requirements on this clock, the routing length for different chip can be different, right?

    Correct. There is no 40 MHz clock skew match requirement across cascaded devices. The frame synchronization is what synchronizes the digital and baseband systems. 

    Thank you,

    -Randy

  • 0 in reply to Randy Rosales
    TI__Mastermind 37726 points

    Randy,

    Thanks a lot for your help! Would you pls help again on below questions?

    Randy Rosales said:

    2. For Digital Frame Sync, as there is already some inter chip imbalance on different chip, I think the length may not vneed to exactly same. Then what's the tolerance of the length difference for Digital Frame Sync?

    The tolerance of the frame sync is the tolerance of the ADC sample window and subsequent CSI-2 data transfer alignment. Increased mismatch will skew the ADC sample windows and skew the CSI-2 transfer times. 

    If customer uses 10Msps ADC sample rate, the sample period will be 100ns. If the tolerance of the ADC sample window is half of the sample period (50ns delay on routing) or more less？

    For the subsequent CSI-2 data transfer alignment, do you mean if there is delay on the frame sync, then the 4-cascaded chips may not output CSI data at same time. This may affect later ADC raw data capture sync. Right? 

  • 0 in reply to Chris Meng
    TI__Mastermind 18500 points

    Hi Chris, 

    I am not sure I understand your sample window question, can you rephrase that?

    Changing the frame-sync delay match will offset the ADC window on each device, but the ADC windows are usually microseconds long though. Well matched routing, with delay differences < 10 picoseconds, should not significantly impact the overlapping ramp seen on each device. PCB routing would have to have significant mismatch to significantly impact ADC sampling window alignment between devices. 

    The frame-sync input start the RF chirp, baseband, ADC and CSI-2 transfer state machine on each device. So yes, the start of the CSI-2 transfers windows from each device will be delay mismatched based on the frame-sync delay. Reception at the host processor will be mismatched by the frame-sync mismatch plus any CSI-2 routing delay differences. 

    Thank you,

    -Randy

    OThannly difference is that hooking this up to a GPIO on the TDA2 host processor that might be going low. 

  • 0 in reply to Randy Rosales
    TI__Mastermind 37726 points

    Randy,

    Thanks for your help. Your below reply answered my question.

    Randy Rosales said:
    Well matched routing, with delay differences < 10 picoseconds, should not significantly impact the overlapping ramp seen on each device.