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AWR1642: Hardware trigger is working,but the current is a little high abnormally

Dawei Wang
Prodigy 40 points
Part Number: AWR1642

Hello everyone,

I'm using the AWR1642 now on the board which designed by ourselves.When i use the software trigger mode,everything works fine.

But right now,when I use the hardware trigger mode to start the frame,I noticed that the current was abnormal.I'm using the advanced frame mode.The first and second subframe periodicity both set to 10ms.When I measured the current with an oscilloscope,I noticed that the current was a little high between the end of subframe periodicity and the next hardware trigger pulse(See Figure 1).So, what i want to know is what is the RSS working status like after the end of subframe and before the next hardware trigger pulse?And why does the current abnormally rise up?On the other hand,with the same setup(except the subframe periodicity), there was not that case with software trigger mode.

Best Regards

Dawei Wang

  • 0
    TI__Guru 58035 points

    Hello Dawei,

    Just before  the end of the programmed periodicity the firmware will turn ON some of the analog blocks so that as soon as the HW trigger is received it can start the chirp. Hence the current is higher from that point. In the example above that period is 10msec. So if the HW trigger actually comes much after 10msec period the current will remain high during that duration. There is no difference in operation in SW triggered mode, just that in SW triggered mode the trigger is generated exactly after 10msec and hence there is a very short extra duration of that higher current state.

    regards,

    Vivek

  • 0 in reply to Vivek Dham
    Prodigy 40 points

    Hi Vivek,

    Thank you for your explanation.It is the same as my analysis.So here's the problem that can I reduce the current during that duration in HW triggered mode?Any APIs can help me to reduce the current?

    Best regards,

    Dawei

  • 0 in reply to Dawei Wang
    TI__Guru 58035 points

    Hello Dawei,

    Keeping the HW trigger pulse periodicity very close to the programmed periodicity (such that it never goes lower than the programmed periodicity) will reduce the period of higher current.

    Regards,

    Vivek

  • 0 in reply to Vivek Dham
    Prodigy 40 points

    Hello Vivek,

    This solution had also been considered.But in my project,the HW trigger pulse need to be triggered after some work like DSP computation,ARM warnning algorithm and so on.Therefore, the HW trigger pulse was not periodic every time,it was generated when these jobs was done.So in this case, I want to reduce the current during that duration ,instead of the period of higher current. Is that possiable?

    Best regards,

    Dawei

  • 0 in reply to Dawei Wang
    TI__Guru 58035 points

    Hello Dawei,

    Unfortunately the reduction in current between the time of programmed periodicity and actual HW trigger is not possible. The device has to be prepared to send out the frame as soon as the HW sync arrives and hence the current is higher. This is true even for SW triggered mode, like I explained in SW triggered mode there is no uncertainty of the trigger point like you have in the DSP, hence you don't observe it.

    Regards,
    Vivek