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TMP116: SCL and SDA signal high/low timing in 6.6 Two-Wire Interface Timing in datasheet

Shunnosuke Maki
Prodigy 320 points
Part Number: TMP116

Hi Teams,

My questions are regarding the Rise / Fall waveform timing of SCL and SDA

1) Why the MIN value is specified only for the SDA Fall time ? 

    Is there any reason why information about the Max value for SDA Rise time is not written on DS ?

2)Are there any concerns if the Fall time is too short?

   Our customers are worried whether some problems can be caused due to length of SDA Data Fall time.

   

Please let me know.

Best Regards,

Maki

  • 0
    TI__Guru* 91206 points

    Dear Maki - 

    Thanks for posting!

    A1. With I2C, the rise times are dominated by the RC time constant the I2C circuit (pullup resistors and bus capacitance) and data is not valid on I2C bus, until SDA is high (and SCL is clocking). So while the parameter you are asking about exists, it is less of the ICs responsibility and more of the circuit designers duty to size the pullup resistors correctly, according to the bus capacitance developed by the actual circuit and the speed of the SCL line (which is controlled by the MCU or MPU acting as the I2C Master. 

    A2. Here they need to refer back to the I2C spec itself, and consider the I2C speed they are operating at. For example, in Standard mode, there is no minimum time for rise or fall of either SCL or SDA, but there is a max, and that would go back to the sizing of the pullup resistor and the bus capacitance of the system. 

    We have really had no reports of I2C timing issues on these devices. If they run into something specific that they can share a schematic and scope captures for, please post again. 

  • 0 in reply to Josh Wyatt
    TI__Prodigy 320 points

    Hi Josh,

    Thank you for your answer.

    Our customers will use TMP116 with Fast-mode.
    TMP116,EEPROM and CPU are connected on the same board in customers' system.

    Customers are worried about shortage of fall time.
    Because,according to DataSheet,fall time is (20 × (V+ / 5.5))= 10.9 ns ,when supply voltage is 3 V.

    Customers' fall time is a few ns.


    >>We have really had no reports of I2C timing issues on these devices. 
    Also, even when Fast-mode or Standard-mode is set, timing issue can not happen?

    Best Regards,

    Maki

  • 0 in reply to Shunnosuke Maki
    TI__Guru* 91206 points

    Maki - 

    Do you have any actual captures of this behavior or any issues seen so far? 

  • 0 in reply to Josh Wyatt
    TI__Prodigy 320 points

    Hi Josh,

    Sorry no, our customers have not had any issues but worried about troubles due to the shortage of Fall time even if they use Fast-mode.

    Could I say we have had no timing issue in this device cleary?

    BRs,

    Maki  

  • 0 in reply to Shunnosuke Maki
    TI__Guru* 91206 points

    Dear Maki -

    As far as we are aware, when developers have followed the specifications, no issues have been seen with the TMP devices. if they have confirmed their MCU is out of spec, the I2C spec gives recommendations to slow it down if it becomes issue, by inserting resistors, etc.