I have modified a few ICBOOST boards to bring the external frame SYNC_IN signal to the SOC and modified the SOC to generate the FRAME_START signal on ball N8 (MCU_CLKOUT).
I've also sent the frameCfg CLI command to enable hardware triggering with 0msec Frame trigger delay.
When using an external high resolution PWM to generate a positive 500ns pulse at exactly 30Hz to trigger a frame start the 6843 only generates 15 frames a second.
This table shows other input (SYNC_IN) to output (FRAME_START) relationships:
|INPUT (Hz)||OUTPUT (frames per second)|
As you can see, there is some magic that happens around 24/25 Hz. If fact if I try and narrow down exactly where the linearity breaks, the SOC stops running (I haven't debugged this as of yet), and this happens at 25 Hz. Scope shows the FRAME_START signal occasionally does not happen after the trigger signal (resulting in the output rates shown above).
As a side note, the configuration for these tests limits targets to about 8 per frame so as to allow for speedy transfer (giving a relatively high frame margin). Software triggering works as expected.
Any insights into this?