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AWR2243: 4 PCS cascaded, LVDS---HS_DEBUG2 pin is useful, don't connect this PIN effect LVDS data trasfer?

Simon wang
Intellectual 410 points
Part Number: AWR2243

Hello,

   I am designing 4 pcs cascaded radar based on AWR2243+FPGA, LVDS of AWR2243 has 7 pair differential line: from timing datasheet of 2243, I don't see HS_DEBUG2, from reference design, these HS_DEBUG2 is LVDS_valid_P/N, I don't know the function of these two pin,   because I/O limited of FPGA, could I don't connect the two pins to I/O of FPGA, that means I only connect clk, 4 pair data, one pair HS_DEBUG1(FRCLK),it effect the data transfer from 2243 to FPGA? 

  • 0
    TI__Guru 58035 points

    Hello Simon,

    The DATA VALID signal (HS_DEBUG2) is high when ever a valid data is been sent out over LVDS interface. But this is not mandatory to use. The Frame Clk (HS_DEBUG1) can be used by the FPGA to detect valid samples also. For example in a 12bit ADC mode the frame clock will remain high for 6 bits and low for 6 bits and when there is no valid data it will not toggle. So  HS_DEBUG2 is redundant in that case.

    Regards,
    Vivek

  • 0 in reply to Vivek Dham
    Intellectual 410 points

    Hello Vivik,

        thanks! another question: LVDS the transfer data speed is fixed? information from datasheet, it only support :

    900 Mbps (450 MHz DDR Clock)

    • 600 Mbps (300 MHz DDR Clock)

    • 450 Mbps (225 MHz DDR Clock)

    • 400 Mbps (200 MHz DDR Clock)

    • 300 Mbps (150 MHz DDR Clock)

    • 225 Mbps (112.5 MHz DDR Clock)

    • 150 Mbps (75 MHz DDR Clock)

    If set ADC 20MSPS, 12bit  complex, the data rate should be 20*12*2=480Mbps, but it seems that no fit rate(LVDS) can be chosed. could you give your great support?

  • 0 in reply to Simon wang
    TI__Guru 58035 points

    Hello Simon,

    You just need to select the LVDS rate that is larger than your raw data rate so that there is no underflow case and before the next chirp of data is available the previous chirp data is already sent out. So in your example you can choose LVDS rate of 600 or 900 Mbps. Once one chirp data transfer is complete the LVDS interface will just wait for the next chirp data to be available before it starts transferring that. So having a larger LVDS o/p data rate is not and issue,

    regards,
    Vivek