TDC7201-ZAX-EVM : Test Board Control Inquiry

Hello,

Welcome to the E2E Sensors Forum!

To clarify, you are initializing the device, but probing the TRIGG1 pin does not show a pulse, and after that you read the TDC1_INT_STATUS register and the COARSE_CNTR_OVF_INT bit is set to 1? Also, no start or stop signal is input to the device?

I have some further questions:

Are you evaluating the EVM using the MSP430F5529 and provided firmware + GUI or with your FPGA?

What happens if you initiate two measurements in series, and do you see the same behavior with TDC1 and TDC2?

Make sure TRIGG1 is probed on TP3 and TRIGG2 on TP6 of the EVM. 

Regards,

Gabriel

Hi !

1. Are you evaluating the EVM using the MSP430F5529 and provided firmware + GUI or with your FPGA?

    - I'm controlling it using the fpga code I made. Do not use msp430f5529 and gui

2. What happens if you initiate two measurements in series, and do you see the same behavior with TDC1 and TDC2?

    - Are you telling me to send signals to tdc1 and tdc2 the same signals to cs1 and cs2?

    - When I used msp430f5529, trig1 reacted normally.

    - I tested it with the same signal of cs1 and cs2, but the result was the same. coarse_cntr_ovf_int err

3. No response to tp3 and tp6 either

I was testing by connecting only the tdc1 related pins. Should I connect all the pins?

Regards,

RYU

RYU,

Each TDC can be used independently, so you can test either TDC1 or TDC2 by itself without making connections to the one not in use, but I would do the following:

Since you have an msp430f5529, I recommend evaluating the EVM basic functionality following the user's guide (or you own customized EVM test). Make sure the board communicates with the GUI and register read/writes are working and probe at least the TRIGGx and INTBx pins during testing. Then test the communication with your FPGA; i.e. write some register settings and see if you can read back the correct values. After that is working, try to replicate the EVM test you did with the MSP430, using your FPGA. 

If you are still seeing issues after this, please provide a schematic or diagram of your FPGA & EVM test setup, along with any additional information/discoveries during testing. 

Regards,

Gabriel

Hi

Thanks to you, I solved it well.

I did the counter counting wrong and it was pushed one by one.

Thanks for the advice :)

Regards,

RYU

Dear Gabriel

I have another question.

I want to use only 100ns of data, so I want to end the measurement after that.

Can I adjust the time when the intb signal changes to a low value by adjusting the value for Coarse_cntr_ovf h&l reg?

If possible, I would appreciate it if you could let me know a simple calculation.
I don't understand the way it's on page 13 of the manual.

have a nice day:)

Regards,

RYU