AWR6843: MSS not getting an abort when accessing the L3 DSS dedicated memory

Francois Charlot

Part Number: AWR6843

Hello,

My customer want to ensure that unwanted MSS accesses to the L2 DSS dedicated memory are properly trapped by an abort exception, but this does not happen.

As per the directions given in the Image Creation document, they set SHARED_MEM_ALLOC to 0x00000006 so to dedicate to DSS all banks 0-5.

They experimented on CCS and the TI EVM. Their code is a test code that on the MSS side accesses all the 0x5100_0000-0x51FF_FFFF range, i.e. all L2 banks from 0 to 7. They did not get an abort at any time and could see on the DSS side that the related MSS write accesses were reflected in the DSS memory window, addresses 0x2000_0000-0x201F_FFFF (They have set a breakpoint on the abort handler and observed that it is never executed.)

This contradicts the technical reference manual that says that "Any access to the DSP-dedicated space by the MSS results in an ABORT".

Could you please help understanding this behavior? Is there something else to configure so to trap such unwanted accesses? Thank you.

Best regards,
François.

over 4 years ago

0 Ishita Kochar over 4 years ago

TI__Mastermind 31680 points

Hello Franois,

Due to Holidays, our experts will be able to get back to your query by next week.

Thankyou for your patience.

Regards,

Ishita

0 Yogesh Siraswar over 4 years ago in reply to Ishita Kochar

TI__Mastermind 20745 points

Hello Francois,

Yes, seems to be a issue. Checking with design team is we are missing anything. Will get back in couple of days.

Thanks

Yogesh

0 Yogesh Siraswar over 4 years ago in reply to Yogesh Siraswar

TI__Mastermind 20745 points

Francois,

Will try and close this offline. Will close this thread.

Thanks

Yogesh

0 Francois Charlot over 4 years ago in reply to Yogesh Siraswar

TI__Mastermind 28237 points

For the sake of the forum readers, as this thread was resolved offline:

The statement in the TRM is misleading.

The MSS may access the L3 MSS/DSS shared banks either through the 0x51XX_XXXX address range through the Arm Cortex R4F main (AXI) bus, or the TCMA (0x002X_XXXX) or TCMB (0x08XX_XXXX) ranges. The TRM should state that if the L3 MSS/DSS shared banks are accessed through the TCMA/TCMB ranges while they are configured as DSS access only, then the MSS will get an ABORT while attempting an access there. However, the MSS will *not* get an ABORT for accesses through the 0x51XX_XXXX range, even if the banks are configured as DSS access only.

The R4F memory protection unit (MPU) may be used to generate such ABORTs if they are required.

Best regards,
François.

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AWR6843: MSS not getting an abort when accessing the L3 DSS dedicated memory