Hello,
I was wondering if it is OK to drive the 40MHz CLKP/CLKM pins on the slave chips of a cascade system using a nominal LVDS 40MHz differential clock, or if this would not be enough voltage swing.
Thanks,
Robert
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Hello,
I was wondering if it is OK to drive the 40MHz CLKP/CLKM pins on the slave chips of a cascade system using a nominal LVDS 40MHz differential clock, or if this would not be enough voltage swing.
Thanks,
Robert
Hello Robert,
You can refer to the section 8.9.3 in the AWR2243 datasheet for the external clock requirements. The clock that is fed should be single ended , should be fed on the CLK P pin while keeping the CLK M pin pulled to Gnd. You can find the clock specification requirements in the datasheet.
Regards,
Vivek