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TMP102: Data hold time is over spec

Jason Dai
Expert 3720 points
Part Number: TMP102

Hello E2E,

Customer uses 257.2kHz i2c frequency on host to communicate to TMP102 and measures data hold time.

The value of data hold time is 2.66us, which is over the maximum spec 900ns.

Could you please tell us how to solve this issue?

~Jason

  • 0
    TI__Guru* 91206 points

    Jason - 

    Do you have any logic analyzer or o'scope captures of what they have measured? 

    is this actually causing an issue? is the controller or any other device on the bus stretching the clock?

     

    How did they pick such a specific frequency? (most folks use 100kHz or 400kHz - just curious on this one, the frequency is OK)

  • 0 in reply to Josh Wyatt
    TI__Expert 3720 points

    Josh,

    Customer is asking if they fails data hold time spec in TMP102. Any risk to cause i2c reading data issue?

    I posted the waveform customer measured below.

    ~Jason

  • 0 in reply to Jason Dai
    TI__Guru* 91206 points

    Jason - 

    here they are not measuring the signal correctly - the tHD;DAT is measured from 30% of the SCL falling edge to 30% of SDA falling edge. The I2C spec is online and free for anyone to view. 

    This would still result in about the same question though, from the screen shots they are showing - which MCU are they using? what does the schematic they have implemented look like? 

    Are they actually having issues, and have they tested their system over their expected operating  temp range? 

  • 0 in reply to Jason Dai
    TI__Mastermind 43905 points

    Hi Jason, 

    There's no issue with violating hold time max as long as other parameters are not violated, (such as setup time for the next clock.) Violating hold time min will cause TMP102 to malfunction.

    thanks,

    ren