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Original question:

PGA411-Q1: Resolver Feedback Disabled, but Chip SPI Working - No Faults Given By Chip

PGA411-Q1: PGA411-Q1 Stuck in Reset State

Derek Cook
Intellectual 880 points
Part Number: PGA411-Q1

Hey all, 

I'm having a pretty big issue in multiple fielded systems containing the PGA411-Q1. What I see is after long power outages, the PGA411-Q1 does not respond to any SPI commands. RESET_N is high. The issue can only be solved by power cycling affected system. There is no SPI communication to the PGA411-Q1 in this failure mode. Cycling RESET_N does not fix the problem. In our application, power cycling the system is very difficult and expensive to do. 

I was able to reproduce this in my lab, and found that when this failure happens Vdd is 300mV and Vext stays at Vcc of 5V. This means that the Vext boost regulator is not enabled, and the MCU is stuck in the reset state. 

Further investigation shows that with RESET_N being low, the difference between the PGA411-Q1 getting stuck in the reset state and working is how soon Vdd turns on with RESET_N low. If the PGA411-Q1 works, Vdd turns to 1.8V in 4.8ms, if PGA411-Q1 does not work, PGA411-Q1 turns to 300msV in 3.2ms. Note that I said that Vdd is turning on when RESET_N is low. Why is this? Documentation shows that Vdd and Vext both turn on in the diagnostic state when RESET_N is high. 

Below is a scope trace showing Vdd when PGA411-Q1 is stuck in reset, Vdd turns on in 3.2ms with RESET_N being low. 

Below is a scope trace showing Vdd when PGA411-Q1 works and Vdd turning to 1.8V in 4.8ms with RESET_N being low. When RESET_N is high,  Vext boost regulator turns on showing the PGA411-Q1 has entered the diagnostic state. Another note, our Vcc rail takes 7ms to reach 5V instead of the defined 4ms in the documentation. But still, I don't understand why Vdd is turning on in the RESET state? 

  • 0
    TI__Expert 3665 points

    Hi Derek,

    All of your images dint make it, can you try uploading them again. Also, during this what is the start of the FAUL pin? Do you have a single supply on VCC and VIO?

    Julio

  • 0 in reply to Julio Apps
    Intellectual 880 points

    It looks like the images did not make it. I attached them here. I have not checked the state of the fault pin. I will check that tomorrow.

    We do have 1 single supply on Vcc and VIO. Do you know why Vdd is on in the RESET state? Documentation shows it should not turn on until the diagnostic state? It looks like it's turning on in the reset state, before our Vcc and Vio power supply is totally ramped. Our Vcc and Vio power supply takes 7ms instead of 4ms to ramp to 5V. 

    Picture 1 - Vdd when pga411-q1 is stuck in reset state

    Picture 2 - Vdd when Pga411-q1 works:

  • 0 in reply to Derek Cook
    TI__Expert 3665 points

    David,

    Thanks for sending this over, yeah im not sure why that may be happening that is not expected behavior.  Sometimes we see issues with having VCC and VIO on the same power supply. Can you check in the sequence of how these ramp up? VIO should never be supplied before VCC is stable. In conditions when VIO is connected to the same 5V source as VCC, the power supply must be able to source at least 400mA of current. 

  • 0 in reply to Julio Apps
    Intellectual 880 points

    Hey Julio, 

    It looks like this is caused because our 5V rail takes longer than 4ms to ramp to 5V. It takes 7ms. We replaced our 5V regulator with a regulator that ramps to 5V within 4ms and the issue goes away. Our regulator we switched to is LM2842XMK-ADJL/NOPB, which is capable of 600mA of current. Our previous regulator was also capable of 600mA of current, but the 5V ramped to 5V within 7ms instead of 4ms.

    I am curious why Vdd comes on in the RESET state though with RESET_N low. That seems like unexpected behavior. You asked about the state of the fault pin. The fault pin is low in the failure mode, shown below. 

  • 0 in reply to Derek Cook
    TI__Expert 7599 points

    I am glad to see that the supply ramp has addressed the issue. In regards to Fault status pin being low indicates that there is a fault in the system... If there are faults in the system it needs to be cleared. 

  • 0 in reply to Arjun_Prakash
    Intellectual 880 points

    The PGA411-Q1 is in the RESET state though. Is the fault pin controlled by PGA411-Q1 in the RESET state? Maybe the fault pin is low due to undervoltage on Vcc because it ramped so slow? 

    Vext boost is not turned on. 

  • 0 in reply to Derek Cook
    TI__Expert 7599 points

    Hello, 

    Here is the document for fault status and more information. 

    There are fault register in DEV_STATx that can be read to understand the faults.  Have you had a chance to read back the registers ? 

  • 0 in reply to Arjun_Prakash
    Intellectual 880 points

    Fixing the 5V power supply ramp solved my issue. Thank you all for the help. 

  • 0 in reply to Derek Cook
    TI__Expert 7599 points

    Glad that helped resolve this.