IWR6843ISK: MSS pin mux

Hello Charles,

Thank you for your answer! I see, and I wonder now if this means that the signals of the pinouts can be changed after having downloaded the firmware into the MSS and DSP, since I assume, from the mmwave Studio configuration tab order, that the pin configuration can be changed after having set the Connection tab up. I thought, as it is done with other ARMs, that the IOs were planed ahead the firmware download, but I might be wrong for this one. Can you confirm this? and have you used this option of port signal mode change?

My intention is to output the Chirp Start, Chirp End and Frame Start from the radar ball pin numbers K13, N8 and P9; so I have a synchronization method when using the LVDS and the ordering of the captured samples. 

BR,

Gorka

Hi,

You can change the GPIO 0 config after sending the MSS and DSS firmware, however the device is development mode  when using MMWAVESTUDIO not functional mode as with the demos.

Not all pins can be configured using the studio interface as you can see. 

I will get back to you to confirm if there is a work around for this.

Regards,

Charles O

Hello again,

I am a little bit confused by your answer, the documentation and the schematics. According to mmwave Studio, which I am using in combination with the setup IWR6843ISK(rev.C)+DCA1000EVM, the possible signals that are transmitted to the DCA1000EVM board are the ones that are seen in the attached figure of the 60pin. In there, no GPIO_0 signal (ball and pin name in the IWR6843 data sheet) can be seen though. Then, how are we supposed to configure the pin to give out the mode we want, but then no signal path is open to the DCA1000EVM. Or, is it the RADAR_DPn called pin signals masking the GPIO0 signal, when using the 60PIN connector to the DCA1000EVM? In that case how can we interpret these RADAR_DPn?

Also, my question is more specific in what it respects to which pin I want to set. My assumption is that the reordering and exact synchronisation of a chirp can only be done when combining the provided LVDS signals, and then other synchronisation signals like CHIRP_START, CHIRP_END and FRAME_START (which are the specific pins commented above - K13, N8, and P9 or GPIO_2, MCU_CLKOUT and PMIC_CLKOUT, respectively). I have not seen either these signals extended into the DCA1000EVM 60pin in the IWR6843ISK rev.C; and I wonder how it can be possible to proper order and count of the samples in a chirp inside the FPGA, without these signals being available.

Let me know if I explain myself, so I can rephrase the part. Thank you!

BR, Gorka

Hi,

The GPIO is configured in studio using the UARR RS232 for register operations. You can in the RegOP tab read and write to/from the registers. This is how the GPIO is configured even though its not routed to the DCA1000EVM header.

mmwave_sdk_03_0x_0x_0x\packages\ti\drivers\gpio\test  shows how to configure GPIO pins, you can try implementing similar register write sequence on studio and confirm if it works.

If this doesn't answer the question can you please clarify what exactly is needed? 

Regards,

Charles O

Hello Charles,

(UPDATED with 1 more point I forgot)

No, this does not answer my question, at least to all the extend of it. Maybe I can rephrase everything in a point based scheme:

1.- What do DPn ports in the 60Pin of the IWR6843 to the DCA1000 mean? Which signals are they, and which is their aim in the system? (look the schematic attached in the comment before)

2.- How does the FPGA make proper alignment of the samples within a chirp, and chirps within a frame if there is not any available signal like CHIRP_START, CHIRP_END and FRAME_START (possible ballpins K13, N8, and P9) routed to the DCA1000EVM? Note that I am asking specifically the step after having clocked properly the bits from the LVDS lanes.

3.- What are SYNC_IN and SYNC_OUT signal used for?

Thank you,

BR

Gorka

HI,

Let me get back to you on this.

Regards,

Charles O

Hello Charles,

Thank you for your response! Some of the questions are resolved for me, but I still miss the part of CHIRP_START, CHIRP_END, and FRAME_START; which I might be misunderstanding from the user guides. So, we have the previously attached 60Pin connector from the IWR6843 to the DCA1000EVM. 

My question is: how does the FPGA order the bytes with the samples, samples within the chirps, and chirps within the frame, if there is only LVDS lanes feeding into the FPGA. For instance, imagine the LVDS, after synchronizing with the radar ADC clock, waits until the FRM_CLK starts. Now, how does the FPGA know that the bits on the lanes are the first ones of a sample (or a chirps, or a frame) if there is no external signal like CHIRP_START, CHIRP_END and FRAME_START fed into the FPGA. There could have been bits loss, and how would the FPGA react or resynchronise to that missing part. Note here that this is not ADC clock synchronisation, but where to find the already clocked bit exact position within the coming raw data. 

I might be missing another important step within the LVDS synchronisation step. Maybe the VALID signal is representing this? Can I have a complete scheme on how the bits are synchronised, and ordered?

Thank you and best regards,

Gorka

Gorka,

Thanks for the clarification, I will reach out to the subject matter expert and get back to you with the feedback.

Regards,

Charles O