IWR6843: LVDS clock always active

Hello user777,

Acknowledged. Allow us couple of days to check in the design, if there is any hooks to disable the clock while data is not being sent. 

Thanks and regards,

CHETHAN KUMAR Y.B.

Hello

We may be able to suggest a register edit which is supported in IWR6843 ES2.0

Can you please confirm the following:

1. Device used is IWR6843 ES.20

2. Which method is used for LVDS data capture:  

mmWave studio    :  Fix may not be applicable.

or

OOB demo : suggested fix can be applied. Will need coding and recompile activity.

Thank you,

Vaibhav

1. Yes, IWR6843 ES2.0

2. OOB demo. Coding and recompiling is not a problem, I know how to do that.

Hi,

Is this the correct way of setting the register?

ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2 = CSL_FINSR (ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2, 3U, 3U, 1U);

I added it to CBUFF_initLVDS, after the write to CFG_LVDS_GEN_1. Unfortunately I don't get any data at all after setting this register to 1. I have verified that DDR clock is used and the first sample is aligned to posedge of the DDR clock.

Hello

Seems like you are using the correct register/bits.  Would you please make sure you have used read modify write and all other bits and configurations are the same between the two runs?

We will try the edit at our end as well.

Thank you,

Vaibhav

Hello,

I am still working on testing this and will provide an update on Monday.

Regards,

Jackson

Hello,

I am still looking into how to change the clock toggling behavior. I have verified that when setting the LVDS_GEN_2[3] bit as you indicate above, the LVDS line stops working. I will provide an update on this feature later this week.

Regards,

Jackson

Hello,

I was able to get the LVDS transfer to work by setting all the other bits in CFG_LVDS_GEN_2 to 0 as below.

ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2 = CSL_FINSR (ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2, 3U, 3U, 1U);
ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2 = CSL_FINSR (ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2, 0U, 2U, 0U); 
ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2 = CSL_FINSR (ptrDriverMCB->ptrCBUFFReg->CFG_LVDS_GEN_2, 4U, 5U, 0U);

This should be the default but writing them all seemed to enable the transfer again. I have not yet verified whether the clock truly stops toggling but will try to verify that tomorrow. In the meantime try adding these writes to your build.

Regards,

Jackson

Hi,

The argument to CSL_FINSR is MSB first, then LSB. So the second and third lines here are setting all bits to 0, including bit 3. In CSL_FINSR, the "bits = (msb - lsb + 1U);" will become 255 if msb is 0 and lsb is 2 for example.

Hi,

Is there any update on the functionality of this register?

Hello,

Sorry for the delay, unfortunately there is no update. You were correct about the arguments of the function, I had them backwards and when corrected, the LVDS data does not seem to transfer. 

Because of the extreme weather and power outages in Dallas, I have not been able to probe the clock or data lines with a scope or analyzer to actually view the behavior. Have you been able to probe the clock line to see if it is not toggling at all? It seems like you did when verifying it lined up with the DDR clock?  Or how are you verifying that there is no data being transferred? I am using our DCA1000EVM and it does not recognize any data, but I can't see the lines.

Regards,

Jackson

Hi,

I have not been able to measure it because I do not currently have access to the tools to do the measurement. I only noticed that I did not get any data after setting the registers. I will try to probe the clock line when I can but it would be nice to have some more things to try if this register does not work.

Do you think it would be possible to keep the LVDS block shut down during interframe period using the MCU and interrupts? Start it up on the frame start interrupt and shut it down again when the frame is done.

Hello,

I was able to measure the LVDS clock with a scope today, both when it is supposed to always toggle and when it should stop unless transmitting. I verified the functionality. After setting the register LVDS_GEN_2 as mentioned before, the LVDS clock toggles for a small time every 200ms, or once every frame. When this bit is not set, the clock toggles the whole time. So it seems the register is indeed working. But I am also no getting any data through the DCA1000 when this register is set. So I think the issue is not the output of data from the IWR6843, but the reception of data. 

What are you using to capture the LVDS data? Is it the DCA1000? I will need a little more time to look into the firmware on this device.

Regards,

Jackson

Hello, sorry for the delay. Are you using the DCA1000 to capture the LVDS data? I realized there is a clause in the DCA1000 user guide about the LVDS clock. It requires 12ms of toggling before sending data to lock the PLL.

"The DCA1000EVM FPGA requires a minimum delay of 12 ms between the bit clock starts and the
actual LVDS data start to lock the LVDS PLL IP."

This seems like it may be a limitation of the FPGA on the DCA1000, but not of the IWR6843. It seems that the clock is toggling intermittently as desired on the scope.

Regards,

Jackson

Hi again,

I am not using DCA1000, I am using custom made HW to receive data. Because neither my HW nor DCA1000 was working I assumed the error was in the IWR6843 device, but I am not certain anymore given your latest comment. I have not been able to measure the clock signal yet to see if it toggles according to the LVDS protocol specification.

A workaround I found was to toggle the register at the start/stop of the frame. When I get the frame start interrupt I set the register to 0, and when the frame is done I set it back to 1. This seems to have solved my problems.