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PGA970: PGA970 5-wires LVDT/RVDT

carmine ricca
Prodigy 150 points
Other Parts Discussed in Thread: PGA970

art Number: PGA970

First of all we would like to bring to your attention the electrical schematic focusing on the LVDT PGA970 connection with the 5 wires LVDT/RVDT secondary side.

LVDT electrical specs are defined as follow:


• 7Vrms excitation (20Vpk-pk on the primary side10Vpk-pk each signal on the secondary side)
• Fex: 3000Hz

As per the above schematic, the LVDT secondary-side signals are properly filtered and partitioned to achieve the PGA970 ADC Input Dynamic (Vrefmax: 2.5V).
The dynamic of the secondary-side signals thereafter becomes about 2.4Vpk-pk with an offset equal to 1.5V. The simulation results are shown below:

We would like to know:

  • Is this the right connection for a 5-wires LVDT/RVDT?

Regarding the SW side we intend to use the PGA970 in RESET MODE and access the data via SPI link (ARM M0 is in RESET MODE).

We would like to know:

  • How can we set S1_S2_CFG ->BIAS_VCM_CONTROL?
  • Based on our conditioning front-end circuit, how can we set S1_CFGàS1_GAIN and S2_CFG S2_GAIN?
  • How can we set S1_CFG->S1_SEM and S2_CFG->S2_SEM

  • 0
    TI__Mastermind 31655 points

    Hi Carmine,

    Please see this example for connecting a 5 wire LVDT.

    Typically you would connect the center tap to the S1N/S2P input as shown in the example above, and enable the VCM pullup on the inputs, with the gain stage set to differential mode. But in your case if you have the center tap and the S1N/S2P grounded, as long as your S1P and S2N is already biased externally, you should not need to use the VCM pullups in the PGA970.

    Note that the single-ended voltage at each pin is limited to 2V on the S1 and S2 gain, so you may need to adjust your bias to maximize the input without clipping. Since your signals are possibly much larger than the input voltage limits of the gain stages, it is best to set the gain to 1. With the configuration in your schematic, you should set each of the secondary inputs to single-ended mode.

    Regards,