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AWR2243: SPI transfer problems:1. the requirements of 2 SPI clocks delay between CS going low and start of SPI clk; 2. HOST ensure a delay of 30us in response to HOST_IRQ interrupt.

Part Number: AWR2243

Hello team,

    I have two questions about SPI of AWR2243:

  1. the max speed of SPI supported is 40MHz, 2 SPI clocks means 50ns delay, but if SPI runs 1MHz, 2 SPI clocks means 2us.  Page 21 of mmWave-Radar-Interface-Control.pdf instructions isn clear because SPI run different speed, 2 SPI clocks means different time, delay 1us is enough for SPI delay between CS going low and start of SPI clk is enough?

2. HOST ensure a delay of 30us in response to HOST_IRQ interrupt.-----this means when HOST receive IRQ, HOST should delay 30us, then reset CS to low, then start SPI clk, is it right?

thanks for your advice.

  • Hi,

    We are checking with HW team and will get back to you

    thank you
    Cesar

  • Dear Cesar,

        Have you get any results? thank you for your help!.

  • Hello Simon,

    Please find my reply below:

    >>  1. the max speed of SPI supported is 40MHz, 2 SPI clocks means 50ns delay, but if SPI runs 1MHz, 2 SPI clocks means 2us.  Page 21 of mmWave->>Radar-Interface-Control.pdf instructions isn clear because SPI run different speed, 2 SPI clocks means different time, delay 1us is enough for SPI delay >>between CS going low and start of SPI clk is enough?

    The SPI CS to CLK delay requirement is in terms of clock cycles, hence two clock cycles delay is needed. In case of lower frequency the absolute time would be larger.

    >>2. HOST ensure a delay of 30us in response to HOST_IRQ interrupt.-----this means when HOST receive IRQ, HOST should delay 30us, then >>reset CS to low, then start SPI clk, is it right?

    The 30usec delay is sufficient to maintain between HOST IRQ going high and host sending a SPI clk. CS could be pulled low earlier.

    Regards,
    Vivek

  • Dear Vivek

         Thanks for your professional instruction. 

         another two questions about AWR2243 configuration:

       1.  about sub block 0x0107----AWR_PROG_FILT_COEFF_RAM_SET_SB:  the materials says it is  one new feature added in awr2243,  this is decimation filter after ADC, this register is used for customer to set decimation filter coefficients by themselves, is it right? that means I have to set these  decimation filter coefficients according to ADC sample rate, then AWR2243 can output right samples value to HOST? or this register have default value and can make sure AWR2243 to output right even if we don't set the two sub block(I mean sub block 0x0107  0x0108)

         I don't know how to configure filter coefficients in fact because I don't know the inner filter architecture in fact . have TI more detailed materials about this section.

    2. about cascaded AWR2243 start sequence, the materials mention: step 2  wait for AWR_AE_DEV_MSSPOWERUPDONE_SB, step 3 send AWR_DEV_RFPOWERUP_SB. but in single device, it should wait for AWR_AE_DEV_MSSPOWERUPDONE_SB, AWR_AE_DEV_booterrorstatus_SB(my system boot  SPI), then send sub block 0x404C(set CRC of ASYNC EVENT), then send AWR_DEV_RFPOWERUP_SB. per my understanding, before configure mater chip and slave chip, cascaded AWR2243 should be same with single device. so I think before step 3 send AWR_DEV_RFPOWERUP_SB, in cascaded mode, host should wait for AWR_AE_DEV_MSSPOWERUPDONE_SB, AWR_AE_DEV_booterrorstatus_SB, then configure sub block 0x404C(set CRC of ASYNC EVENT), then send AWR_DEV_RFPOWERUP_SB, is it right?

  • Hello Simon,

    1) The use of the programmable filter is only when you want to bypass in the internal anti aliasing filter and want to create your own filter. Else by default we have a very good anti aliasing filter design which can be used in most uses case. If you use the default filter you don't have to issue the programmable filter API.

    2) On the power sequence, are you referring to the ICD or the DFP example for this sequence?

    Regards,
    Vivek