Team, customer is asking if AWR1843 UART can support 3M Baud rate?
They cannot find this info in our documentation.
Thanks
V
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Team, customer is asking if AWR1843 UART can support 3M Baud rate?
They cannot find this info in our documentation.
Thanks
V
Hi Cesar,
Thanks for the answer.
Our software/firmware engineers didn't touch the VCLK clock configure part. The default VCLK = 50MHz, and 50M/16 = 3.125MHz; we want 3M, so the VCLK would be 48MHz.
Then how to configure the VCLK to 48MHz? Meanwhile we also need to use the CAN-FD (the only two I/O we care.)
Regards,
Kevin
Hello Kevin,
Can you take a look at the below e2e posts about configuring the UART baud rate and let us know if this helps?
Regards,
Adrian
Hello Adrian,
To me, the problem is not to reduce the baudrate; the problem is how to set the baudrate to exactly at 3M.
To set the baudrate to be 3M, the VCLK needs to be 3MHz x 16 x (n+1) = 48MHz, 96MHz .... and so on, where the n = 0, 1, 2, ...
If you set:
gMmwMssMCB.cfg.sysClockFrequency = MSS_SYS_VCLK;
gMmwMssMCB.cfg.loggingBaudRate = 3000000;
without change the setting of the MSS_SYS_VCLK;
Assuming the MSS_SYS_VCLK = 50MHz, then you can get BaudRate = 3125000 only.Hello Kevin,
You can set the VCLK source to the 240MHz PLL clock by setting VCLKCLKSRCSEL to a value of '011'.
Then set the VCLKCLKDIV clock divider value to a value of 5 and this should give you a clock of 48MHz.
Regards,
Adrian