Hi,
I am working on a project as an FPGA developer where I have to receive data from 4 cascaded AWR2243s and I am using LVDS interface to do so.
My question is: Knowing that they are cascaded (they share the 20GHz clock), is there a way to synchronize LVDS clocks and data reception of all 4 chips (or at least 2), so that I can receive the data using only one clock (not 4)?
Otherwise, having multiple clocks on the same data reception path in the FPGA is a limiting factor for the data flow design.
Ivan
