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AWR2243: What‘s the max delay or phase gap between 4 LO traces in 4-chip cascaded system?

Chris Meng
Mastermind 37736 points
Part Number: AWR2243
Other Parts Discussed in Thread: MMWCAS-RF-EVM

My customer simulated TI LO design on 4-chip cascaded system (MMWCAS-RF-EVM). They found there are still some phase gaps on LO traces. Customer wants to know what‘s the max delay or phase gap between 4 LO traces in 4-chip cascaded system which will not affect the RF performance.

 Would you pls kindly help?

  • 0
    TI__Guru 58035 points

    Hello Chris,

    The mismatch in the LO delay of the 4 chips does not impact RF performance. How much of delay mismatch can be tolerated depends on the algorithm used by the customer. In many cases this phase mismatch can be compensated for in the processing just like how the channel to channel phase mismatch is compensated for in a radar sensor.

    Regards,

    Vivek