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AWR1843: DSS startup fail on POR reset from MSS

Vinoth Kumar Elangovan
Prodigy 10 points
Part Number: AWR1843

Hello,

I am working with the AWR1843 sensor. I'm trying to reset the DSP core from MSS.

I am able to restart the DSP core, however the core registers are not initialized. The program counter does not have the address of the main(). It always point to 0x007E0000 after the restart.

I checked the program memory in L2 and it seems to be loaded correct. 

Is there a way to ensure the reinitialization of registers upon DSP restart?

  • 0
    Prodigy 10 points

    An update regarding my query. The L2 memory seems to be erased. 

    I checked MSS#42 in AWR1843 Errata. My issue could be probably related to this. It says:

    1. Set the GEM_CLK_EN_BYPASS_CTRL bit in the TOPRCM-> GEMPWRSMCFG2
    register Bit 7 as ‘1’.
    2. Set the GEM_GRSTN_GATE_BYPASS_CTRL bit in the TOPRCM->
    GEMPWRSMCFG1 Bit 9 register as ‘1’.
    3. Write a value of 0xFFFF in , DSS_REG ->L2MEMINITCFG1 register.
    4. Write a value of 0xF in , DSS_REG ->L2MEMINITCFG2 register
    5. Write a value of 0x0 in TOPRCM-> GEMPWRSMCFG1-> PWRSMOUTBYPCTRL
    register.

    But I can't seem to find the following registers. TOPRCM-> GEMPWRSMCFG2, TOPRCM->GEMPWRSMCFG1.

    Could you please check and update?

  • 0 in reply to Vinoth Kumar Elangovan
    TI__Guru*** 148954 points

    Hi,

    Our expert will provide you this information

    Thank you

    Cesar

  • 0 in reply to Cesar
    TI__Mastermind 24955 points

    Information has been provided. This thread will now be closed.

    Regards,
    Kyle

  • 0 in reply to Kyle Cousino
    Prodigy 10 points

    I found a discrepency in the errata #42 procedure. 

    In step 2 bit 9 should be set to 1 in TOPRCM->GEMPWRSMCFG1.
    However, in step 5 TOPRCM-> GEMPWRSMCFG1-> PWRSMOUTBYPCTRL which accounts for bits 23:0 should be cleared. This will clear the 9th bit set in step 2 as well.

    Is my understanding correct? 

    I performed errata #42 procedure during the power down of the DSS. However, this did not resolve my issue.

    The issue:

    After reset, when the DSS is powered ON, the core registers are not reset corrrectly. The Program counter points to the starting address of L2 memory. Others registers also are not reset correctly. 

    Because of this, after reset, the DSS cannot resume the execution of the program.

  • 0 in reply to Vinoth Kumar Elangovan
    TI__Mastermind 24955 points

    This issue is being handled offline. This thread will be closed on this forum.

    Regards,
    Kyle