IWR1843: Error when running SPI EVM to EVM test

Chris Meng

Part Number: IWR1843

Hi,

I tried to run Test_XWR1xxxWithXWR1xxx with two xWR1843BOOSTs. I tried default lib and the lib I rebuild with multi icount enabled (#define SPI_MULT_ICOUNT_SUPPORT).

But I met error when the bitrate is bigger than 20Mhz. Pls find error log below.

default spi lib:

Fullscreen spi_EVMtoEVM_error_log1.txt Download

[Cortex_R4_0] ******************************************
Debug: MibSPI Driver Test Application Start 
******************************************
Feature: SPI_open API test (instance=0): Passed
Debug: SPI Instance @0800fe6c has been opened successfully
Debug: SPI Instance @0800fe6c has been closed successfully
Debug: Passed DMA channel number check
Feature: SPI_open API test - DMA channel validation (instance=0): Passed
Feature: SPI_open API test - chip select validation (instance=0): Passed
Feature: SPI_open API test - data size validation (instance=0): Passed
Feature: SPI_open API test - bit rate validation (instance=0): Passed
Debug: Open the SPI Instance for SPI transfer parameter check test
Debug: SPI_transfer with data size = 1 failed with error=6.
Feature: SPI_transfer API test - data size=1 validation (instance=0): Passed
Debug: SPI_transfer with data size = 11 failed with error=6. 
Feature: SPI_transfer API test - data size=11 validation (instance=0): Passed
Debug: SPI_transfer failed with NULL pointers for both TX and RX. 
Feature: SPI_transfer API test - buffer address validation (instance=0): Passed
Debug: SPI Instance @0800fe6c has been closed successfully
Debug: Finished API Test for SPIA!
Feature: SPI_open API test (instance=1): Passed
Debug: SPI Instance @0800fe78 has been opened successfully
Debug: SPI Instance @0800fe78 has been closed successfully
Debug: Passed DMA channel number check
Feature: SPI_open API test - DMA channel validation (instance=1): Passed
Feature: SPI_open API test - chip select validation (instance=1): Passed
Feature: SPI_open API test - data size validation (instance=1): Passed
Feature: SPI_open API test - bit rate validation (instance=1): Passed
Debug: Open the SPI Instance for SPI transfer parameter check test
Debug: SPI_transfer with data size = 1 failed with error=6.
Feature: SPI_transfer API test - data size=1 validation (instance=1): Passed
Debug: SPI_transfer with data size = 11 failed with error=6. 
Feature: SPI_transfer API test - data size=11 validation (instance=1): Passed
Debug: SPI_transfer failed with NULL pointers for both TX and RX. 
Feature: SPI_transfer API test - buffer address validation (instance=1): Passed
Debug: SPI Instance @0800fe78 has been closed successfully
Debug: Finished API Test for SPIB!
Debug: SPI Instance(0) @0800fe6c has been opened successfully
Debug: SPI Instance(1) @0800fe78 has been opened successfully
Feature: SPI_open API test for two instances: Passed
Debug: SPI Instance(0) @0800fe6c has been closed successfully
Debug: SPI Instance(1) @0800fe78 has been closed successfully
Debug: SPI Instance(0) @0800fe6c has been opened successfully
Debug: passed DMA channel number check for two SPI instances.
Feature: SPI_open API test for two instances: DMA channel validation: Passed
Debug: SPI Instance @0800fe6c has been closed successfully
Debug: Finished API Test for SPIA + SPIB!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 0.9363 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 0.9363 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 1000 Kbps : Passed
Debug: 4pin mode 1MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 1.7589 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 1.7589 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 2000 Kbps : Passed
Debug: 4pin mode 2MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 4.2767 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 4.2767 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 6000 Kbps : Passed
Debug: 4pin mode 6MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 5.9228 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 5.9234 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 10000 Kbps : Passed
Debug: 4pin mode 10MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 8.4140 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 8.4120 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 20000 Kbps : Passed
Debug: 4pin mode 20MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 10.6430 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 10.6445 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0

spi lib with multi icount enabled:

Fullscreen spi_EVMtoEVM_multi_icount_error_log1.txt Download

******************************************
Debug: MibSPI Driver Test Application Start 
******************************************
Feature: SPI_open API test (instance=0): Passed
Debug: SPI Instance @0800fe6c has been opened successfully
Debug: SPI Instance @0800fe6c has been closed successfully
Debug: Passed DMA channel number check
Feature: SPI_open API test - DMA channel validation (instance=0): Passed
Feature: SPI_open API test - chip select validation (instance=0): Passed
Feature: SPI_open API test - data size validation (instance=0): Passed
Feature: SPI_open API test - bit rate validation (instance=0): Passed
Debug: Open the SPI Instance for SPI transfer parameter check test
Debug: SPI_transfer with data size = 1 failed with error=6.
Feature: SPI_transfer API test - data size=1 validation (instance=0): Passed
Debug: SPI_transfer with data size = 11 failed with error=6. 
Feature: SPI_transfer API test - data size=11 validation (instance=0): Passed
Debug: SPI_transfer failed with NULL pointers for both TX and RX. 
Feature: SPI_transfer API test - buffer address validation (instance=0): Passed
Debug: SPI Instance @0800fe6c has been closed successfully
Debug: Finished API Test for SPIA!
Feature: SPI_open API test (instance=1): Passed
Debug: SPI Instance @0800fe78 has been opened successfully
Debug: SPI Instance @0800fe78 has been closed successfully
Debug: Passed DMA channel number check
Feature: SPI_open API test - DMA channel validation (instance=1): Passed
Feature: SPI_open API test - chip select validation (instance=1): Passed
Feature: SPI_open API test - data size validation (instance=1): Passed
Feature: SPI_open API test - bit rate validation (instance=1): Passed
Debug: Open the SPI Instance for SPI transfer parameter check test
Debug: SPI_transfer with data size = 1 failed with error=6.
Feature: SPI_transfer API test - data size=1 validation (instance=1): Passed
Debug: SPI_transfer with data size = 11 failed with error=6. 
Feature: SPI_transfer API test - data size=11 validation (instance=1): Passed
Debug: SPI_transfer failed with NULL pointers for both TX and RX. 
Feature: SPI_transfer API test - buffer address validation (instance=1): Passed
Debug: SPI Instance @0800fe78 has been closed successfully
Debug: Finished API Test for SPIB!
Debug: SPI Instance(0) @0800fe6c has been opened successfully
Debug: SPI Instance(1) @0800fe78 has been opened successfully
Feature: SPI_open API test for two instances: Passed
Debug: SPI Instance(0) @0800fe6c has been closed successfully
Debug: SPI Instance(1) @0800fe78 has been closed successfully
Debug: SPI Instance(0) @0800fe6c has been opened successfully
Debug: passed DMA channel number check for two SPI instances.
Feature: SPI_open API test for two instances: DMA channel validation: Passed
Debug: SPI Instance @0800fe6c has been closed successfully
Debug: Finished API Test for SPIA + SPIB!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 0.9363 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 0.9363 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 1000 Kbps : Passed
Debug: 4pin mode 1MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 1.7589 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 1.7588 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 2000 Kbps : Passed
Debug: 4pin mode 2MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 4.2759 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 4.2766 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 6000 Kbps : Passed
Debug: 4pin mode 6MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 5.9259 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 5.9240 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 10000 Kbps : Passed
Debug: 4pin mode 10MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 8.4142 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 8.4043 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 20000 Kbps : Passed
Debug: 4pin mode 20MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 10.6480 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 10.6442 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0

I have two questions. Would you pls help?

1. The issue happens with higher clock. Is it due the line I connected two boards are too long? Pls find my setup below.

2. Why the throughput with and without multi icount enable is similar? I suppose when multi icount enabled, the throughput should be higher?

over 4 years ago

0 Vaibhav Mahimkar over 4 years ago

TI__Mastermind 23725 points

Hello

Are you saying the feature works upto 20Mbps and after that you see fails.

Is the fail seen during receive or transmit?

Thank you,

Vaibhav

0 Chris Meng over 4 years ago in reply to Vaibhav Mahimkar

TI__Mastermind 37716 points

Vaibhav,

The error is from receive side. It can't receive correct data.

0 Akash Gondalia over 4 years ago in reply to Chris Meng

TI__Guru 50240 points

Hi Chris

Can you confirm Vaibhav's first comment? That it does work up to 20Mbps?

Regards,

0 Chris Meng over 4 years ago in reply to Akash Gondalia

TI__Mastermind 37716 points

Akash,

If you checked the log file I shared, you will find below info. So the test with 20MHz clock works ok. And then failed with 40Mhz clock test.

Debug: 4pin mode 20MHz passed!
Debug: SPI Instance @0800fe6c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 10.6430 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 10.6445 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=9a2b, dataLen=32776, seq=0

For this test, I removed the comment for multi icount support definition as below to rebuld the spi lib.

C:\ti\mmwave_sdk_03_05_00_04\packages\ti\drivers\spi\src\mibspi_dma.c

#define SPI_MULT_ICOUNT_SUPPORT

For test code of SPI master, I did below modification.

C:\ti\mmwave_sdk_03_05_00_04\packages\ti\drivers\spi\test\xwr18xx\main.c

/* Test case global variables */
bool gXWR1xxxLoopbackTest =false;

bool gXWR1xxxSlaveReady = false;

/* Test with MSP43x */
bool gXWR1xxxMasterWithMSPTest = false;
bool gXWR1xxxSlaveWithMSPTest = false;

/* Test with PC through FTDI */
bool gXWR1xxxSlaveWithFTDITest = false;

/* Test with XWR1xxx */
bool gXWR1xxxMasterWithXWR1xxx = true;
bool gXWR1xxxSlaveWithXWR1xxx = false;

For test code of SPI slave, I did below modification.

C:\ti\mmwave_sdk_03_05_00_04\packages\ti\drivers\spi\test\xwr18xx\main.c

/* Test case global variables */
bool gXWR1xxxLoopbackTest =false;

bool gXWR1xxxSlaveReady = false;

/* Test with MSP43x */
bool gXWR1xxxMasterWithMSPTest = false;
bool gXWR1xxxSlaveWithMSPTest = false;

/* Test with PC through FTDI */
bool gXWR1xxxSlaveWithFTDITest = false;

/* Test with XWR1xxx */
bool gXWR1xxxMasterWithXWR1xxx = false;
bool gXWR1xxxSlaveWithXWR1xxx = true;

I made a mistake in previous test with multi icount support enabled. I missed to remove the comment for multi icount support in test_common.c. I rebuild the test code today and tried again.

C:\ti\mmwave_sdk_03_05_00_04\packages\ti\drivers\spi-m\test\common\test_common.c

#define SPI_MULT_ICOUNT_SUPPORT

Below is latest log.

Fullscreen spi_EVMtoEVM_multi_icount_error_log_0429_2.txt Download

******************************************
Debug: MibSPI Driver Test Application Start 
******************************************
Feature: SPI_open API test (instance=0): Passed
Debug: SPI Instance @0801056c has been opened successfully
Debug: SPI Instance @0801056c has been closed successfully
Debug: Passed DMA channel number check
Feature: SPI_open API test - DMA channel validation (instance=0): Passed
Feature: SPI_open API test - chip select validation (instance=0): Passed
Feature: SPI_open API test - data size validation (instance=0): Passed
Feature: SPI_open API test - bit rate validation (instance=0): Passed
Debug: Open the SPI Instance for SPI transfer parameter check test
Debug: SPI_transfer with data size = 1 failed with error=6.
Feature: SPI_transfer API test - data size=1 validation (instance=0): Passed
Debug: SPI_transfer with data size = 11 failed with error=6. 
Feature: SPI_transfer API test - data size=11 validation (instance=0): Passed
Debug: SPI_transfer failed with NULL pointers for both TX and RX. 
Feature: SPI_transfer API test - buffer address validation (instance=0): Passed
Debug: SPI Instance @0801056c has been closed successfully
Debug: Finished API Test for SPIA!
Feature: SPI_open API test (instance=1): Passed
Debug: SPI Instance @08010578 has been opened successfully
Debug: SPI Instance @08010578 has been closed successfully
Debug: Passed DMA channel number check
Feature: SPI_open API test - DMA channel validation (instance=1): Passed
Feature: SPI_open API test - chip select validation (instance=1): Passed
Feature: SPI_open API test - data size validation (instance=1): Passed
Feature: SPI_open API test - bit rate validation (instance=1): Passed
Debug: Open the SPI Instance for SPI transfer parameter check test
Debug: SPI_transfer with data size = 1 failed with error=6.
Feature: SPI_transfer API test - data size=1 validation (instance=1): Passed
Debug: SPI_transfer with data size = 11 failed with error=6. 
Feature: SPI_transfer API test - data size=11 validation (instance=1): Passed
Debug: SPI_transfer failed with NULL pointers for both TX and RX. 
Feature: SPI_transfer API test - buffer address validation (instance=1): Passed
Debug: SPI Instance @08010578 has been closed successfully
Debug: Finished API Test for SPIB!
Debug: SPI Instance(0) @0801056c has been opened successfully
Debug: SPI Instance(1) @08010578 has been opened successfully
Feature: SPI_open API test for two instances: Passed
Debug: SPI Instance(0) @0801056c has been closed successfully
Debug: SPI Instance(1) @08010578 has been closed successfully
Debug: SPI Instance(0) @0801056c has been opened successfully
Debug: passed DMA channel number check for two SPI instances.
Feature: SPI_open API test for two instances: DMA channel validation: Passed
Debug: SPI Instance @0801056c has been closed successfully
Debug: Finished API Test for SPIA + SPIB!
Debug: SPI Instance @0801056c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 0.9635 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 0.9635 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 1000 Kbps : Passed
Debug: 4pin mode 1MHz passed!
Debug: SPI Instance @0801056c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 1.8574 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 1.8574 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 2000 Kbps : Passed
Debug: 4pin mode 2MHz passed!
Debug: SPI Instance @0801056c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 4.9115 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 4.9107 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Feature: SPI 4Pin mode Master test at bitRate 6000 Kbps : Passed
Debug: 4pin mode 6MHz passed!
Debug: SPI Instance @0801056c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 7.2029 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 7.2011 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=56c9, dataLen=23129, seq=22615
Master: recv msg: magic=56cb, dataLen=23129, seq=22615
Master: recv msg: magic=56cd, dataLen=23129, seq=22615
Master: recv msg: magic=56cf, dataLen=23129, seq=22615
Master: recv msg: magic=56d1, dataLen=23129, seq=22615
Master: recv msg: magic=56d3, dataLen=23129, seq=22615
Master: recv msg: magic=56d5, dataLen=23129, seq=22615
Master: recv msg: magic=56d7, dataLen=23129, seq=22615
Master: recv msg: magic=56d9, dataLen=23129, seq=22615
Master: recv msg: magic=56db, dataLen=23129, seq=22615
Master: recv msg: magic=56dd, dataLen=23129, seq=22615
Master: recv msg: magic=56df, dataLen=23129, seq=22615
Master: recv msg: magic=56e1, dataLen=23129, seq=22615
Master: recv msg: magic=56e3, dataLen=23129, seq=22615
Master: recv msg: magic=56e5, dataLen=23129, seq=22615
Master: recv msg: magic=56e7, dataLen=23129, seq=22615
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=96
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=96
Data test failed for loop=96
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=200
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=200
Data test failed for loop=200
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=216
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=216
Data test failed for loop=216
Data test failed for loop=262
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=263
Data test failed for loop=274
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=275
Data test failed for loop=301
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=302
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=390
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=390
Data test failed for loop=390
Data test failed for loop=502
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=503
Data test failed for loop=520
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=521
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=538
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=538
Data test failed for loop=538
Data test failed for loop=549
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=550
Data test failed for loop=559
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=560
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=592
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=592
Data test failed for loop=592
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=651
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=651
Data test failed for loop=651
Data test failed for loop=705
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=706
Data test failed for loop=864
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=865
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=931
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=931
Data test failed for loop=931
Feature: SPI 4Pin mode Master test at bitRate 10000 Kbps : Passed
Debug: 4pin mode 10MHz passed!
Debug: SPI Instance @0801056c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 11.2649 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 11.2641 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=56e2, dataLen=23129, seq=22615
Master: recv msg: magic=56e4, dataLen=23129, seq=22615
Master: recv msg: magic=56e6, dataLen=23129, seq=22615
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=3456, dataLen=16, seq=1
Master: Synced with Slave, start data echo test
Data test failed for loop=28
Master: Incorrect in Msg: magic =0xffff, dataLen=65535, seqNo=65535, loop=29
Feature: SPI 4Pin mode Master test at bitRate 20000 Kbps : Passed
Debug: 4pin mode 20MHz passed!
Debug: SPI Instance @0801056c has been reopened in MASTER mode successfully
Master: Start SPI Write test with XWR1xxx
Master write Throughput = 15.7152 Mbps
Master: Start SPI Read test with XWR1xxx
Debug: Master read Throughput = 15.7104 Mbps
Master: Start SPI Data echo test with XWR1xxx
Master: recv msg: magic=ab6c, dataLen=44332, seq=11307
Master: recv msg: magic=ab6d, dataLen=44332, seq=11307
Master: recv msg: magic=ab6e, dataLen=44332, seq=11307
Master: recv msg: magic=ab6f, dataLen=44332, seq=11307
Master: recv msg: magic=ab70, dataLen=44332, seq=11307
Master: recv msg: magic=ab71, dataLen=44332, seq=11307
Master: recv msg: magic=ab72, dataLen=44332, seq=11307
Master: recv msg: magic=ab73, dataLen=44332, seq=11307
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=ffff, dataLen=65535, seq=65535
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0
Master: recv msg: magic=9a2b, dataLen=32776, seq=0

Now I can see the throughput is higher with multi icount support enabled.

But I can see there are some errors with10/20Mhz test and it also failed in 40Mhz test.

Would you pls help to check why there is error in high frequency test?

0 Chris Meng over 4 years ago in reply to Chris Meng

TI__Mastermind 37716 points

Akash,

Any update?

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IWR1843: Error when running SPI EVM to EVM test