AWR1243: Question about LVDS Valid

Chris Meng

Part Number: AWR1243
Other Parts Discussed in Thread: AWR1443, , AWR1642

Hi,

In AWR1243 datasheet, I can't find detail info of pin definition for LVDS. In AWR1443 EVM schematic, I found HS_DEBUG1 is for LVDS_FRCLK and HS_DEBUG2 is for LVDS_VALID.

I found a LVDS timing in Figure 13-5. LVDS Interface Timings of swru520.pdf (awr14_16_trm), but there is no info about LVDS valid signal. Would you pls kindly advise the timing of LVDS Valid?

over 7 years ago

0 Vivek Dham over 7 years ago

TI__Guru 58035 points

Hello Chris,
In case of AWR1243/1443 there is an additional data valid LVDS signal available but this is actually redundant and need not be used. Just like in case of AWR1642 the data validity can be got using the frame clock it self. When ever there is valid data on the LVDS lanes the frame clock would be toggling.

Regards,
Vivek

0 Vivek Dham over 7 years ago in reply to Vivek Dham

TI__Guru 58035 points

Hello Chris,
Did this help clarify your doubt?

Regards,
Vivek

0 Chris Meng over 7 years ago in reply to Vivek Dham

TI__Mastermind 36705 points

Vivek,

My customer wants to have a signal to know when the ADC frame starts and ends. Can the LVDS data valid to show such info? Will it continue to be active during the whole adc/chirp frame data transfer?

I draws a timing of lvds data valid signal as below. Would you pls help to check if it is correct?

0 Vivek Dham over 7 years ago in reply to Chris Meng

TI__Guru 58035 points

Hello Chris,
The LVDS data valid is high for one "packet" which is typically one chirp data, not one frame. But since the host knows the chirp configurations he can look for number of chirps and derive the frame boundary.

Regards,
Vivek

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AWR1243: Question about LVDS Valid