UCC24612: early turn-off

Hirotsugu Kobayashi

Part Number: UCC24612
Other Parts Discussed in Thread: UCC28782,

Hi team,

We are evaluating UCC24612-1 in combination with UCC28782.
A phenomenon occurred where the product turned off early at maximum output. There is no waveform that could cause malfunctions such as ringing.
Is there any way to improve it?

Best regards,

7 months ago

0 Mike O' 7 months ago

TI__Guru* 77495 points

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

0 Mike O' 7 months ago in reply to Mike O'

TI__Guru* 77495 points

Hello,

If the Idson*Rdson is less than 10 mV the gate drive will shutoff.

Regards,

0 Hirotsugu Kobayashi 7 months ago in reply to Mike O'

Mastermind 9105 points

Hi Mike,

I will check Idson.

I have placed the parts according to the recommended layout, but is there anything that could be improved?

Best regards,

0 Ning Tan 7 months ago in reply to Hirotsugu Kobayashi

TI__Expert 6005 points

Kobayashi san,

Here are few threads for your reference.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/679062/ucc24612-ucc24612-switch-turn-off-early

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/741810/ucc24612-sr-premature-turning-off-and-the-gate-drive-voltage-reduces-function-is-not-always-happend

Best,

Ning

0 Hirotsugu Kobayashi 7 months ago in reply to Ning Tan

Mastermind 9105 points

Hi Ning,

Thank you. I will check the threads.

Could you comment about layout?

Best regards,

0 Ning Tan 6 months ago in reply to Hirotsugu Kobayashi

TI__Expert 6005 points

Kobayashi san,

you could also try to the placement below.

Best,

Ning

0 Hirotsugu Kobayashi 6 months ago in reply to Ning Tan

Mastermind 9105 points

Hi Ning,

I can't see the attached file.
Could you please re-attach it?

Best regards,

0 Ning Tan 6 months ago in reply to Hirotsugu Kobayashi

TI__Expert 6005 points

Please see this image below.

0 Hirotsugu Kobayashi 6 months ago in reply to Ning Tan

Mastermind 9105 points

Hi Ning,

With this layout, it appears that the FET source and IC VS are placed close together, even if the distance between the FET drain and the IC VD terminal is sacrificed.
Is my understanding correct?

0 Mike O' 6 months ago in reply to Hirotsugu Kobayashi

TI__Guru* 77495 points

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

0 Mike O' 6 months ago in reply to Mike O'

TI__Guru* 77495 points

Hello,

Could you send a schematic and the layout in electronic format so we can review it?

Regards and thanks,

Mike

0 Hirotsugu Kobayashi 6 months ago in reply to Mike O'

Mastermind 9105 points

Hi Mike,

Our design is arranged so that the Gate is the shortest.

The layout you proposed is arranged so that the Source is the shortest.

Which layout do you recommend?

0 Mike O' 6 months ago in reply to Hirotsugu Kobayashi

TI__Guru* 77495 points

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

0 Mike O' 6 months ago in reply to Mike O'

TI__Guru* 77495 points

Hello,

The following link will bring you to the UCC24612 will bring you to an evaluation module with a proven layout.

I would suggest you use this layout.

https://www.ti.com/lit/ug/sluubp3/sluubp3.pdf

I would also suggest that you put place holders for an R and C snubber across the FET's drain to source. Those components are actually present in the example layout above. The User's guide above also gives instructions on how to setup this snubber.

Regards,

0 Hirotsugu Kobayashi 6 months ago in reply to Mike O'

Mastermind 9105 points

Hi Mike,

As in the example provided by Ning, when I made the source and Vs as short as possible and sensed the drain with wiring, it worked as expected.
The actual layout is subject to various constraints.
The source and VS connection is different in the data sheet and EVM.
Is it correct that the basic layout is to make the source and VS, and the gate and Vg as short as possible, and to route the drain with wiring?

0 Mike O' 6 months ago in reply to Hirotsugu Kobayashi

TI__Guru* 77495 points

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

0 Mike O' 6 months ago in reply to Mike O'

TI__Guru* 77495 points

Hello,

You are correct that shorter traces are better. You will add roughly 10 nH of inductance per inch. So shorter is better.

From your hand drawing you sent of the layout it looks like the traces from the UCC24612 to the FETs drain to source could me be much short. However, if your design is working now then maybe you don't have to adjust your layout.

Regards,

0 Hirotsugu Kobayashi 6 months ago in reply to Mike O'

Mastermind 9105 points

Hi Mike,

I have written down the actual pattern and placement location.
Is it recommended to minimize the Source and VS and route the Drain?

0 Mike O' 6 months ago in reply to Hirotsugu Kobayashi

TI__Guru* 77495 points

Hello,

I am reviewing your inquiry and will get back to you shortly.

Regards,

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

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UCC24612: early turn-off