Dear team
Does TI have such an analog switch?
The system defaults to the slave clk path, which can be switched when the analog switch detects that the master clk has a signal.
When the analog switch detects that the master clk has no signal, it can switch back to the slave clk.
Many thanks
Denny
Hi Denny,
We don't have any single chip solution that can do this. However it should be pretty easy to implement with a few parts.
Above is shown a system that meets the goals of the application. It is a generic viewpoint so many different switches can fit. The idea is that the select pin will be driven high any time the primary clock is active and it will be driven low otherwise.
It works by buffering the primary clock signal into a 2nd order RC low pass filter. In this instance we want the DC value of the clock signal so cutting the frequency with a cutoff of 10MHz should be sufficient to get DC level at the output of the filter. This DC value is then compared with a voltage divider from VDD (in my quick simulation I found R3 = 2k and R4 = 1k seemed to work but this may be slightly different when using real comparators versus ideal ones). If the output of the filter is greater than the voltage divider the comparator will output a high signal telling the multiplexer that the primary path is active and needs to be chosen.
When the primary signal is turned off the output of the comparator will be 0V which will select the secondary clock again.
However my question now is - how many channels do you need? I see that the TMUX1575 was tagged in this post - which could work with this implementation but the all 4 switches would be controlled by the primary clock's presence.
Do you need a 4 channel 2:1 switch ? Or are you looking for a 1 channel 2:1 switch? Also what voltage supplies and signal levels are you expecting in your application - I want to make sure that you have the best IC for the application - so please let me know and I will see what I can do!
Best,
Parker Dodson
