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TMUX6111: Power sequencing

Rose Rehfeldt
Prodigy 40 points
Part Number: TMUX6111

Hello,

In section 11 of the datasheet, it is recommended to ramp Vss prior to Vdd in a dual supply setup for the TMUX6111.  Is this because of the potential for back-powering behavior or is there another reason?

Thank you,

Rose

  • 0
    TI__Mastermind 43115 points

    Hi Rose,

    The most important aspect is still to ensure a proper GND connection before either supply is brought up. 

    Its not back-powering as this is a specific line out of the TMUX611X datasheet that isn't present in the similar TMUX721X datasheet - which are very similar parts with respect to architecture. Back-powering in multiplexers really happens when a signal at the input is greater than VDD or less than VSS causing the ESD diodes to conduct allowing the input signal to become more or less a "source" - so ramping VSS first really shouldn't cause back powering as no live signals really should be on the input until the supplies are stable at the operating point of the device since this device does not have powered-off protection. 

    I am working with our design team to see why this recommendation is there - it isn't something that is usually mentioned so we are verifying if there is any difference in this part compared to our other mid-voltage multiplexers why this would be the case. Its a bit complicated as an older design team handled this part so it will take a bit of time to find the answer - but we should have some information by 9/30/21, but if I receive the information earlier I will be sure to pass it on. 

    With that all being said though - the most important consideration is to have a solid ground connection first before either supply is ramped as no ground connection and ramping supplies could damage/destroy the device. 

    If you have any questions in the mean time please let me know and I will see what I can do!

    Best,

    Parker Dodson

  • 0
    TI__Mastermind 43115 points

    Hi Rose,

    So our design team was able to simulate the silicon to see why this may be an issue.

    1. We didn't simulate any issue when VDD was ramped up first.

    2. Our teams best guess is that across process and temperature there is less chances for glitches at power up - but if its not followed it doesn't seem to be a huge risk.

    Best,

    Parker Dodson