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TMUX1136: Latched condition with high current draw from the VDD pin

Doug Young
Intellectual 315 points
Part Number: TMUX1136

I have a design that uses the TMUX1136 to switch a fiber optic receiver module (photo diode) between two amplifier circuits.  We have been using this circuit successfully for a couple of years but on the latest build something has changed where the TMUX1136 will sometimes draw a lot of current and get very hot.  The condition persists until power is removed from the board.  If power is reapplied to the board, the condition does not come back immediately.

It appears that the condition only occurs when the receiver is receiving data.  Under this condition, the common input (D1) to the TMUX1136 can be biased < 0V.  We have tried to emulate the failure condition by pulling D1 below -0.5V and were able to get the part to sink large currents after pulling D1 < -1.0V, but this was not a latched condition.  The TMUX1136 returned to normal operation after D1 was released.

Given that in the application D1 input can be pulled below 0V, but not typically below the max rating of -0.5V, could the TMUX1136 latch up in a high current condition?  Given the connections to the part, the current must be flowing from VDD to GND internal to the TMUX1136.

Any insight that you can provide would be appreciated so that I can work on a solution to this issue.

Here is a link to a FLIR image of the board while the TMUX1136 is locked up.  The TMUX1136 is the bright yellow box in the lower left quadrant of the board.

https://drive.google.com/file/d/1vQmhVowBljIYx1p7Hx2_8XdaB5bRcwc3/view?usp=share_link

Sincerely,

Doug Young

  • 0
    TI__Genius 10974 points

    Hi Doug,

    Latchup can occur when these devices see an injection of current or an overvoltage event. Tying the D pin to some negative voltage will not necessarily induce this latchup event as this is simply just turning on the diode between the input and GND and this is expected behavior when you put the device in that condition (VIN < -0.5V). To replicate what you are seeing, there is likely a transient event occuring on the initial data trasmission that is taking the pin overvoltage/undervoltage rapidly and exposing the device to a large amount of current. Have you tried taking any scope shots of the D pin during this data transmission? That may give some better insight on what is being exposed to the device.

    Thanks!

    Bryan

  • 0 in reply to Bryan Marshall
    Intellectual 315 points

    Hi Bryan,

    We've only gotten the condition occur on a couple of boards.  We did look at the D1 pin on a board that doesn't present the issue and it would transition between 0V and around -250mV while receiving data packets.  The boards that fail may be different, especially if their photo diodes are higher gain than on the boards that don't exhibit the behavior.

    The 2nd switching element on the TMUX1136 switches between a net pulled down to ground through a 499K resistor (S2B)  and +2.8V (S2A). All of the analog switch nets connected to the TMUX1136 are high impedance, at least 40K Ohm, with the exception of the one pin connected to the photo diode and that net is not expected to be able to sink high current.

    I can share with you the schematic page that contains the switch through a private message.

    Sincerely,

    Doug Young

  • 0 in reply to Doug Young
    TI__Genius 10974 points

    Hi Doug,

    A schematic would be helpful. I am a bit confused on your statement on how the boards that fail are different? In what way exactly? You mention that the photo diode gain may be different? How significantly different and how much current draw are you expecting?

    Let me know if you can provide further details on this.

    Thanks!

    Bryan

  • 0 in reply to Bryan Marshall
    Intellectual 315 points

    Hi Bryan,

    Sorry for the delay, I somehow missed that you had replied last week.

    I can see how my last message may have caused some confusion.  I was trying to say that there may be something different about the boards that failed due to an unknown component value change or manufacturing defect.  There are no intentional design differences.  As far as the difference in photo diode gain, again that is pure speculation to explain how the D1 pin minimum voltage could be at a level below the -500mV limit specified in the datasheet.

    I can share the schematic with TI but it is proprietary so I won't post it to the public forum.  Can you send me a private message or email for sharing the schematic?

    Sincerely,

    Doug Young

  • 0 in reply to Doug Young
    TI__Genius 10974 points

    Hi Doug,

    I will message you and we can take this conversation offline.

    Thanks!

    Bryan