SN74CBTLV3245A: The OE state when power-off

Bin Pan

Part Number: SN74CBTLV3245A

In our design, we use CPLD to control the OE of SN74CBTLV3245APWR. CPLD set high level（3.3V) when SN74CBTLV3245APWR is power-off and the drive strength of CPLD is 9mA, Will SN74CBTLV3245APWR be damaged in this case？ If will, can decrease the drive strength of CPLD to avoid this risk？

over 2 years ago

0 Clemens Ladisch over 2 years ago

Guru 316690 points

This is allowed; see [FAQ] Can the input voltage (Vi) to my logic device be higher than the supply voltage (Vcc)?

0 Alex Vish over 2 years ago

TI__Genius 10552 points

Hi Bin,

As Clemens mentioned with the FAQ, this device does support input voltages up to 3.6V when Vcc=0 (device power off). Looks like you will have no issues using the device under the conditions mentioned here.

Let me know if I can be of further assistance here!

Thanks!

Alex

0 Bin Pan over 2 years ago in reply to Alex Vish

Prodigy 20 points

Thanks for your responds! Another question: EN remains high(3.3V), Is there any risk at the moment of VCC power-on?

0 Alex Vish over 2 years ago in reply to Bin Pan

TI__Genius 10552 points

Hi Bin,

Ramping Vcc here while EN remains high will not cause an issue either. The powered-off protection feature protects the device in this case.

Thanks!

Alex

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SN74CBTLV3245A: The OE state when power-off