the data sheet show a Typical D-PHY Application about one dsi output to two mipi module, but we want use it as two mipi output to one module.
we want to use it to address LP Bi-direction Communication problem with our fpga which does not support LP Bi-direction transmit.
our hard dphy0 can only send LP single direction, but with ip function problem, we can not use it send LP command and read. so we need use another LP port to realize LP receive and send command.
