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TMUX646: How to achieve CSI differential impedance of a 100 ohms with a BGA CSI switch?

Mohamed Mohamed
Prodigy 10 points
Part Number: TMUX646

Hello, 

I'm currently working on a layout for connecting two CSI interface cameras (15 pin and 24 pin) and I'm utilizing the switch to switch between the two. I'm struggling to match the impedance to 100 ohm differential impedance. My current PCB specs are as follows: 
  • Trace thickness: .035 mm
  • Dielectric height: 0.21 mm
  • Trace width: 3 mils
  • Trace spacing: 4.1 mils 
  • er = 4.2
  • Resulting differential impedance: 138 ohms
Now, I'm trying to increase my trace width to 6 mils and make the spacing 3 mils which would give me a Zdiff = 100 ohms. My questions are as follows:
1. Can I fan out the BGA traces at 3 mils then increase the trace width to 6 mils. How significant will the impedance mismatch be? Is this a common practice when dealing with small pitch BGA's
2. Should I instead use multiple in-pad vias and run 6 mil traces (less desirable) in order to avoid the impedance mismatch when changing trace widths from 3 mils to 6 mils? 
3. Is it okay if solution in question 2 is more desirable to run a differential pair on different layers? (ie D0_N on top layer and D0_P on bottom layer)?
4. I can also get a 100 Zdiff with a trace width of 3 mils and trace spacing of 1 mil. But that would introduce undesired cross coupling. Is this true or is 1 mil okay? 
I also attached my current BGA layout. 
  • 0
    TI__Mastermind 18095 points

    Hello Mohamed,

    I am not a high speed PCB designer, but here are a few suggestions regarding your concerns.

    Also I linked a high speed layout consideration guide we have: https://www.ti.com/lit/an/slla414/slla414.pdf

    Now regarding your questions:

    1. Yes this is common practice with BGA packages. There will be slight miss match on the differential pair. You will want to minimize the miss match length and make sure both traces on the differential pair are symmetric in terms of mismatch and length.
    2. No, vias themselves can cause impedance mismatches. Best minimize those on your board.
    3. You can, but it will defeat the purpose of noise rejection of the differential pairs. 
    4. I would avoid doing so, since it is a very small spacing between the traces and I can't guarantee if it will work. 

    Here is another source to check out for high speed design: https://s3vi.ndc.nasa.gov/ssri-kb/static/resources/High-Speed%20PCB%20Design%20Guide.pdf 

    Thanks,

    Nir