TMUXS7614D: Leakage current issue

Hello Jeffrey,

The SDO pin has an internal pull up resistor to VL. This creates a resistor divider between the internal pull up and the resistance on the SDO line from the MCU. Resulting in 2.4V before the SPI communication.  

It is not clear to me of where the 20nA leakage is measured. Is it on the I/O or the SPI control pins?

Thanks,

Nir

Hi Nir,

Nir Gilgur said:

The SDO pin has an internal pull up resistor to VL. This creates a resistor divider between the internal pull up and the resistance on the SDO line from the MCU. Resulting in 2.4V before the SPI communication.  

SDO pin is connected to SDI pin due to daisy-chain mode. Please check it again and let me know. And do you know an internal pull up resistor value to VL?

Let me explain how the leakage current is measured. Please see a first page of attachment. For example, PMU_Sensing(S1) port is connected to 1414COM_1(D1), and 1414COM_1(S1 of 2nd IC) port is connected to IO_CH1(D1 of 2nd IC) through daisy-chain control. Also, PMU_Forcing(S2) port is connected to 1414COM_2(D2), and 1414COM_2(S1 of 2nd IC) port is connected to IO_CH1(D1 of 2nd IC) through daisy-chain control. There are some typos on the right side of first page, the net name of 1414COM_x is correct as 1414COM_2. As a result, PMU_Sensing and PMU_Forcing are connected to the connector. And then they are input to PMU, to ADC, to FPGA, and the leakage current is measured through FPGA program tool. Is it clear?

Please let me know if you need more information to check this issue.

Regards,

Hello Jeffrey,

Understood, can the customer monitor and probe the VL supply node (SPST_VL) and the SDO node before and after SPI communication? I want to check how the supply behaves. 
The internal pull up resistor value is 4MΩ.

Thank you for the explanation, it is clear. 

According to the schematic you have the drain pins and source pins shorted. This will increase your overall leakage and add it up linearly. 
What is the operating temperature of this application? 

Thanks,

Nir 

Hello Jeffery,

Another thing could be if the customer is using a passive scope probe, its input impedance is 10MΩ typical.
From the voltage divider created: 3.3 x 10M/(10M +4M) ~2.4V

Thanks,

Nir 

Hi Nir,

Please check my answers below about your questions.

Can the customer monitor and probe the VL supply node (SPST_VL) and the SDO node before and after SPI communication? Yes, VL supply node is all same 3.3V before and after SPI communication, but SDO node is different before(2.4V) and after(3.3V) SPI communication. It is totally opposite against AGDS1414D. Is there any other reasons about it?

According to the schematic you have the drain pins and source pins shorted. This will increase your overall leakage and add it up linearly. 
What is the operating temperature of this application? It is 35C. Customer thinks that overall leakage current of ADGS1414D should be increased because it is same configuration shorted between the drain pins and source pins, but the actual measured overall current is much lower than TMUXS7614D. Could you explain about it?

Regards,

Hello Jeffery,

Can you please confirm with the customer about the probe? 

The current measurements are different between the two parts is most likely because of difference in architecture and process. 
What is the voltage used to measure the leakage current on the TMUX and ADG devices?

Thanks,

Nir 

Hi Nir,

Please check my answers below about your questions.

Can you please confirm with the customer about the probe? It is N2862B passive probe with input resistance of 10Mohm.

What is the voltage used to measure the leakage current on the TMUX and ADG devices? It is measured under condition of VDD=15V, VSS=-15V, VL=3.3V. Please check the schematic of attachment above.

Regards,

Hi Nir,

Nir Gilgur said:

So, the reason the customer is seeing 2.4V on the signal is due to the probe creating a voltage divider. 

I understood what you mean. one more thing, could you explain the reason why SDO voltage level is different before and after SPI communication?

Regards,

Hi Nir,

I understood what you mean, but it is 3.3V on the SDO line after SPI communication. Please let me know why.

Regards,

Hello Jeffery,

My assumption is because before sending the SPI signal there is a High Z on the line of 4MΩ due to the pull-up resistor. After sending the signal the line is no longer High Z and there is no voltage divider. 

I have reached out to our designer to confirm my assumption. I will let you know what he says when I get his input.

Thanks,

Nir 

Hi Nir,

Please confirm your assumption after checking with the designer.

Regards,

Hello Jeffery,

Will do, waiting on a response from the design engineer.

I will update you as soon as I receive it.

Thanks,

Nir 

Hello Jeffery,

Can you please confirm the state of the CS line when reading 3.3V on SDO? 

SDO will be hi-z (4Mohm pulled up) if /CS=H.
SDO pin driven by CMOS buffer if /CS=L

Thanks,

Nir 

Hi Nir,

The state of CS line is low when reading 3.3V on SDO. Also, did you get a response from design engineer?

Regards,

Hello Jeffery,

This question came from the design engineer.

I will relay your response to him and update you with his answer.

Thanks,

Nir