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Original question:

SN74AUC2G53: SN74AUC2G53 break-before-make time

SN74AUC2G53: Achieving 1 to 4 fanout: best practices within AUC logic family?

John Silzel
Prodigy 10 points
Part Number: SN74AUC2G53
Other Parts Discussed in Thread: SN74AUC1G74, LMK1C1104

Tool/software:

I am doing a new design for a quadrature sampling detector in which an incoming RF signal must be sampled four times in one cycle.  This requires switching the (analog) signal to a capacitor for integration over a 10 nsec integration period.  For this reason, a 1 nsec switch transition time already introduces a 10% signal loss in this stage-- my sense is that only the AUC family switches can meet my need.

The question is this:  

My candidate design requires me to drive up to four SN74AUC2G53 control inputs (A) from the outputs  (Q or /Q) of an SN74AUC1G74.  I plan to place the '53s and '74 on the same PCBA with less than 2" trace distance, max.  How do you recommend implementing a 1 to 4 fan-out in AUC logic while maintaining the best signal integrity at the driven inputs?  I assume there must be a best practice since I am interfacing all TI products within the same logic family?

There are no 1:4 Fan Out Buffers in the AUC logic family that would let me drive 4 switches from independent driver stages.  I could drive a 50 ohm line, end terminated at the 4th switch and accept some skewing of the control clock arrival at each of the switch stages, perhaps.

Thank you for suggesting a "best practice" here.

John

  • 0
    Guru 298340 points

    There are 1:4 clock buffers like the LMK1C1104, but I do not think they would be an improvement over just driving all four control inputs directly from the logic output.

    If you want to avoid skew between the inputs, use four traces of the same length.

    AUC outputs are optimized for traces with a characteristic impedance of 50 Ω, but an actual 50 Ω resistance would be too large a load.

  • 0 in reply to Clemens Ladisch
    Prodigy 10 points

    Thank you Clemens for the quick response. 

    Are you saying the AUC output on the 1G74 can simply be fanned out (with same trace lengths to manage skew) to as many as 4 AUC inputs without regard for external termination components, as with legacy logic families? 

    In this case the output would see the parallel equivalent impedance of the traces and 4 loads, and the output would of course be driving 4x the (nominal 2 pF) capacitive load of one control input, so about 8 pF. 

    This would sure be simple if the AUC driver allows it.

  • 0 in reply to John Silzel
    Guru 298340 points

    CMOS inputs have a very high impedance. The datasheet specifies output parameters for a load of 15 pF; a typical input has 2.5 pF. (A very rough estimate of trace capacitance is 1 pF/cm.)

    You can route the trace to the switches, and then split into four stubs with the same length.

    For short traces, the impedance does not matter. (A rule of thumb is that a trace is short if it is no longer than two inches per nanosecond of rise/fall time.)

    AUC outputs dynamically adjust their impedance and should not be used with additional termination.

  • 0 in reply to Clemens Ladisch
    Prodigy 10 points

    Thanks very much, I will give that a go.