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SN74CB3Q3244: Power Down Impedance

Chris Krasnichuk1
Prodigy 640 points
Part Number: SN74CB3Q3244

Tool/software:

Hi Folks

Looking at the SN74CB3Q3244 IC (8 Bit FET Bus Switch) in a design and want to permanently enable its output by pulling down the OE pin of the IC. In the datasheet, two separate statements related to device condition in power down are given:

1) During power down, The device provides isolation using its IOFF circuitry and the I/Os can tolerate up to 5V.
2) OE should be tied to VCC through a pull-up to ensure high impedance state during power down.  

Can we clarify that with permanent pull down at OE, during & after power down does this IC offer high impedance between its input & output (Source & Drain of FET switch) ?

  • 0
    TI__Genius 17745 points

    Hello Chris,

    With a permanent pull down at OE we cannot guarantee the device will be in high impedance mode. Since the device is enabled low, the switches might close.  

    I recommend tying the OE to a pull up, so the switches will be in a predictable high impedance state. 

    Thanks,

    Nir 

  • 0 in reply to Nir Gilgur
    TI__Prodigy 640 points

    Thanks Nir, A quick follow up:

    """

    Since it is recommended to pull up the OE so that the switches will be in a predictable high-impedance state during or after power down.

    So, this means OE should be pulled up from a different supply, rather than the VCC supply of the device. Can you please clarify this also?

    """

  • 0 in reply to Chris Krasnichuk1
    TI__Genius 17745 points

    Hello Chris,

    Yes, you are correct.

    The datasheet says "OE should be tied to VCC" which it is confusing, but it basically means OE should be pulled high. 

    Thanks,

    Nir