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SN74CB3Q3244: Power Down Impedance

Part Number: SN74CB3Q3244

Tool/software:

Hi Folks

Looking at the SN74CB3Q3244 IC (8 Bit FET Bus Switch) in a design and want to permanently enable its output by pulling down the OE pin of the IC. In the datasheet, two separate statements related to device condition in power down are given:

1) During power down, The device provides isolation using its IOFF circuitry and the I/Os can tolerate up to 5V.
2) OE should be tied to VCC through a pull-up to ensure high impedance state during power down.  

Can we clarify that with permanent pull down at OE, during & after power down does this IC offer high impedance between its input & output (Source & Drain of FET switch) ?