TMUX7201: Potentially incomplete PSPICE models

Hi Linh,

Looking at the model currently online it actually looks to have the  Delay_SW_S1D1

I also tested the model

And When I ran the model in pspice it worked

Can you tell me more about your setup and I can see if I can repeat the failure or just see what you are seeing?

Regards,

Kameron

Hello Kameron,

Thank you so much for the response. I recreated the exact circuit you're using to test the model and still got the same error. I am using Cadence for my simulation - not sure if this could be the reason why it's returning this error?

Sincerely,

Linh

Hi Linh,

I think this might be the where the issue is.

I am not familiar with taking a pspice file and using it in cadence but I am looking into it and seeing that it could be tricky to actually do.

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/47414/pspice-model-simulating-in-cadence-virtuoso

To start off is there any possibility you would be able to use the TMUX7201 pspice in pspice for TI as that is what we evaluate these models in strictly?

Please let me know and I can help 

Regards,

Kameron

Hi Kameron,

I need Cadence for my simulation unfortunately... I tried 2 things: (1) removing the NC output (there are currently 2 of them in the model) and (2) removing the line where the error occurred (X_U14 SW_S1D1_L VDD GND SW_S1D1 Delay_SW_S1D1) and the simulation ran fine (the output was wrong though).

I am not sure if this helps with the troubleshooting. Nonetheless, the error Cadence gave seems to suggest that 'Delay_SW_S1D' was mentioned in pspice code but was not defined anywhere. That's why when I remove the line that contains 'Delay_SW_S1D' it ran without error...

Please let me know if that gives you some idea/if there's anything else I could try on my end.

Sincerely,

Linh

Hi Linh,

After looking into this further your intial thoughts were correct that the model was missing the Delay_SW_S1D1 subckt block.

This missing text doesn't effect simulations when running this device in pspice but from my teams understanding this could affect other environments you use the model in 

This is the text that I added to this file which should fix the error

 *BUFFER
.SUBCKT Delay_SW_S1D1 IN VDD GND OUT
*
C1 OUT_ONDLY GND 1e-09
ERON NRON GND TABLE {V(VDD,GND)} =
+ (12,10.0)
+ (15,10.0)
+ (20,10.0)
+ (44,10.0)
R1 OUT_ONDLY IN 10e9
GRON OUT_ONDLY IN VALUE = {V(OUT_ONDLY,IN)/V(NRON)}
*
EOUT_ONREC OUT_ONREC GND VALUE = { V(OUT_ONDLY, GND)}
*
S_ON OUT_ONREC OUT IN GND SWON
.MODEL SWON VSWITCH Roff=1e9 Ron=0.001 Voff=0.37V Von=0.63V
*
C2 OUT_OFFDLY GND 1e-09
EROFF NROFF GND TABLE {V(VDD,GND)} =
+ (12,21.519)
+ (15,21.519)
+ (20,21.519)
+ (44,21.519)
R2 OUT_OFFDLY IN 10e9
GROFF OUT_OFFDLY IN VALUE = {V(OUT_OFFDLY,IN)/V(NROFF)}
*
EOUT_OFFREC OUT_OFFREC GND VALUE = { V(OUT_OFFDLY, GND)}
*
S_OFF OUT_OFFREC OUT IN GND SWOFF
.MODEL SWOFF VSWITCH Roff=1e9 Ron=0.001 Voff=0.63V Von=0.37V
*
.ENDS

Here is the file where I made this addition.

Copy of TMUX7201.lib

Try this file and see if this works in cadence

If not I can take another look and make some more edits

Please let me know if this helps!

Regards,

Kameron

Hi Kameron,

My apologies for the delayed response.... The new .lib file fixed that error!! Thank you so much for your support!!

However, it now returns another error to me:

Error found by spectre in `TMUX7201', during circuit read-in.
ERROR (SFE-1):  Found duplicate terminal name `NC' in the definition of subcircuit `TMUX7201'.

Do you have any suggestions on this issue?

Sincerely,

Linh

Hi Linh,

Good to here we are getting closer to the model working here!

So looking into this I think the only thing we have to do is just change the  one of the NC pin names( I changed NC it to NC1  and this should fix the issue in cadence)

The NC pins are not electrically connected to the actual model blocks inside the TMUX7201

This is issue seems to be common in cadence but I think this should be a easy fix.

Copy of Copy of TMUX7201 (1).lib

Please let me know if this works and we can take another look if not

Hi Kameron,

Thank you so much for the suggestions! I changed one of the NCs to NC1 as you suggested and now the simulation can run without any error!!

One issue arose after this though... I tried testing this switch using the exact circuit that you used above in your pspice sim. However instead of reading ~ 3V for the V(R1) mine reads ~ 0V. I am not sure what might be causing this discrepancy?

Sincerely,

Linh

Hi Linh!

I think the discrepancy is potentially due to myself having a older version of pspice where the TMUX7201 had the incorrect logic control( It was opposite of the datasheet but this issue was fixed in the model released online late last year.

Could you try to put a logic low signal on the select 1 pin in your design

This should allow the signal to pass through the switch.

Please Let me know if this helps.

Regards,

Kameron