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TMUX1101: Regarding OFF leakage of TMUX1101

Part Number: TMUX1101

Tool/software:

Hello TI support,

We are trying to use TMUX1101 in gain switching application. However, the PSpice model doesn't seems to provide OFF leakage as per datasheet when tried to test as per datasheet conditions. It gives more leakage even in actual circuit. Could you please check & advise whether,

1. OFF/ ON leakages are modelled in the model.

2. If those are modelled then not sure why it appears 100nA in test circuit? Is there anything being missed from my side?

3. Also how will the OFF leakages change when VSource=0 to 3.3V & Vdrain=3.3 to 0 when supplies are 3.3V. Datasheet conditions are with VS=1V/3V & VD= 3V/1V. Also it will be appreciated if this data is available over -40'C to +85'C.

Regards,

JK

       

  • Hi JK,

    Looks like it isn't modeled in the circuit so your values not being accurate makes sense. Looks like ROFF is 10e6 and It's probably using that to give you the leakage (V/R).

    Whether 3.3/1 or 3.3/0 perform better really depends on the device and will depend on the leakage paths. They could be the same or in some instances, as it does feel intuitively, you would see the 3.3/0 having a little extra leakage. I'll run it by our designer that is on this part though and see what they think. They are on a work travel currently though so it may be a delayed response.
    In the meantime, I'll look into what information I can find for the leakage across temp that we may have already collected.

    Thanks,
    Rami

  • Hello Rami,

    Thanks for this information. I shall further await your response with pertaining details.

    Regards,

    JK

  • Hello Rami,

    Not sure if the designers you mentioned are back, just checking if there are any further updates on this thread.

    Regards,

    JK

  • Hi JK,

    Sorry for the delay. I'm still looking to see if someone on the team has some remnants of the leakage across temp data.


    As for the 3.3/1V leakage tests, the feedback I got was that generally the signal chain doesn't actually use rail-to-tail voltages due to the headroom requirements of opamps and/or ADC's that are in the signal path. So we spec'ed it at a normal condition. The IOFF will be larger though at 3.3V/0V since the drop across the switch will be greater and the voltage on the ESD will experience the same, causing a higher leakage. We unfortunately don't have that specified though.

    -Rami

  • Hello Rami,

    Yes, both rails are not required but 0V is included in our case. Not sure if it is feasible to specify some rough number for 3V/0V or 3.3V/0V?

    Regards,

    JK 

  • Hi Jk,

    So we were able to find 3V/0V simulation data at 25C and saw about 2nA off leakage. This is simulation though and not something guaranteed by design. 
    I was finally able to also find some across temp data. From a small sample size of our validation data, it looks like the max across temp (at 125C) we saw was about 60pA.

    Thanks,
    Rami

  • Hello Rami,

    Thanks for providing this information. However, I am curious about these questions,

    1. As the online models were in question for modelling leakage currents, not sure if the models you used that gave 2nA were different from the one available online? Please advise.

    2. I hope 60pA data is for 3V/0V case? If that is the case then 60pA leakage at 125'C is appears quite less compared to max 0.9nA specified at 125'C. May be this is because of sample size? 

    Regards,

    JK

  • Hi Jk,

    1. The design models are far more complex then the one you have online and used only by our internal design team so I would expect them to be more accurate. The model you're using looks like didn't take leakage into consideration when developing the model. 

    2. Unfortunately, it's going to be the 3V/1V case. Across temp at the 3V/1V case the variation wasn't that large and it should translate closely to the 3V/0V case. I can't give you any direct numbers though since we haven't run it. I think you would really either want to evaluate it yourself or assume some buffer when designing it in. A couple nA across temp seems to be a safe amount extra to anticipate for, although there's a chance we would see even less. Sorry, we just don't have the data though to give an confident estimation. 

    Thanks,
    Rami

  • Hello Rami,

    Got it and thanks for your support till now answering each query.

    Regards,

    JK