Other Parts Discussed in Thread: SN74LVC1G17, TLV810E, TMUX1219
Tool/software:
Could you please clarify a discrepancy between specifications in the data sheet and the typical application circuit.
The data sheet for the SN74LVC1G3157 shows that the recommended operating conditions include a 20 ns/V maximum rise and fall rates for the control input.
In addition, it also draws attention to the Application Report titled "Implications of Slow or Floating CMOS Inputs".
I understand why slow rise and fall times should be avoided with non-Schmitt-trigger CMOS inputs.
But then Section 15.2 of the data sheet (Typical Application) shows a schematic that definitely violates the maximum rise and fall conditions, as it shows an RC delay circuit driving the logic input that would certainly have rise and fall times in the range of tens of milliseconds in any practical application.
So what is the situation? Are slow rise and fall times acceptable on the logic input of the SN74LVC1G3157, or not?
(By the way, I intend to use the SN74LVC1G3157 driven from an open-drain device; the fall time will certainly be fast but the rise time will be in the hundreds of nsec region.)