I am using the ACH4066 in a new design that is sensitive to I/O capacitance. More specifically, my design is more sensitive to one side of the switch than the other.
The data sheet states 5.5pF typical capacitance per I/O. In looking at the simplified schematic on the data sheet it looks like the "B" side of the switch would have less capacitance than the "A" side. Should I favor the "B" side to minimize capacitance? What values should I use? What kind of variance should I expect on the nominal values?
Also, I assume that the 5.5pF is measured in the high impedance state. Is a C-R-C PI configuration, where C is 5.5pf a suitable model for the ON state? Is there a more appropriate distributed model?
