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They are evaluating our TS3A27518E between WIFI and SD card but they faced some fail issue with SD card3.0(SDR104). I saw the DC offset with high data rate clock. How do I remove the DC offset with high data rate? 2 scope snippets are attached - the first without TS3A27518E and the second with TS3A27518E
Chip input trace Parasitic Capacitanceè 0.05pF, Output Trace Parasitic Capacitanceè 0.1pF at 1.8V VDD
Ranita,
Am I correct seeing that the top image without the TS3A27518E on the board and has a signal 0 to 1.6V? Does the bottom image show a signal probed at the COM1 pin yellow and NO1 pin green range 0.4V to 1.4 V?
Do you think that there is too much capacitance for the signal to get down to 0V before the clock goes high and the signal is getting attenuated? Or do you think there is a DC offset voltage being introduced to the signal?
The signal you are running looks to be about 200MHz which is approaching -3dB loss. I think you may be seeing bandwidth limitation and you amplitude is decreasing: 1.6 V x 0.707 (-3dB) = 1.13 V instead of a offset voltage. To fix this you can try increasing the voltage of the signal to overcome the amplitude loss through the switch.
Thank you,
Adam
