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SN74CBT16214C: Is an Output Load required on these devices?

Bill Trautman
Prodigy 30 points
Part Number: SN74CBT16214C
Other Parts Discussed in Thread: SN74CBT16214

I have tested many FET based analog switches in the past and none of them have worked satisfactorily for me as they always seem to bleed signal when the switch is turned off and the output is run into a high impedance circuit, particularly when running at a high frequency.  This can also cause a mix of signals between the turned ON FET switch with that of the turned OFF FET switch if the outputs are tied together as would be the case in a 2:1 (SPDT) switch configuration.  Do the FET switches in the SN74CBT16214C act similarly?  If so, is there a recommended resistive and/or capacitive load required if running into high impedance gates?  Alternatively, is there a similar 1:3 or 1:4 demux or a 3:1 or 4:1 mux based upon standard AND/OR gate logic that I could use for this purpose with several switches in a package (12 in a package would be nice like the SN74CBT16214C has)?  Thanks. 

  • 0
    TI__Expert 3900 points

    Hi Bill,

    Regarding your first comment. To clarify, you are talking about when is switch is disconnected or if the entire device is powered-off? If you are referring to the latter then the SN74CBT16214C has a feature called powered off protection, essentially stating the max current flow into a channel when Vcc = 0V.

    Can you also clarify your statement regarding the correlation between running into high impedance, particularly at high frequency. Also, what frequency are you operating at?

    You mentioned using a device like the SN74CBT16214 but one that uses AND/OR logic instead of FET based switching. Is your end application switching digital signals?

  • 0 in reply to Dakotah
    Prodigy 30 points

    I'm sorry if I wasn't clear in my original post.  My end application is to switch digital signals, not analog, at least at this time.  I would like to run the output of this chip into digital logic gate inputs (high impedance). 

    I am not talking about using the device while powered down.  Rather, with standard power applied to the device but a particular FET switch set to "OFF", I wondered if input signal will bleed to the output if the output is not sufficiently loaded, and if so, what sort of a load would be required to minimize this bleed.  When I mentioned operating at a high frequency, I was saying that the higher the frequency, the greater the tendency analog switches bleed signal...at least in my experience.  I'm talking about using this device around 1MHz.  Thank you.

  • 0 in reply to Bill Trautman
    TI__Expert 3900 points

    Thanks for the clarification on your end application. The spec you are referring to for our FET based switches is called Off-Isolation which states the attenuation in dB  when the device is powered and a switch is turned off. Unfortunately this is not spec'd in this datasheet. I have attached a snippet of a different device datasheet to show you what the spec looks like for future use of FET based switches.

    It seems that you are worried about the voltage present on your downstream digital logic inputs. More specifically having potential bleed-through of signal trigger a change from a logic low to a logic high or vice versa. One option to solve this with FET based switches is to look at our portfolio of buffered encoders and decoders.

      

    I'll also pass the thread on to the experts in our digital logic controlled switches.

  • 0 in reply to Dakotah
    Prodigy 30 points

    Thank you.  That is what I was looking for.  Also looking at the OFF Isolation spec from the datasheet of that other device, it shows quite a low load impedance (50 Ohms).  This is what I figured the SN74CBT16214C might need in order to minimize bleed and in my application this would be unacceptable.  Yes, I am concerned about bleed signals causing a change of my downstream logic gates.  I will look at the listing of buffered encoders and decoders.  Again, thanks.