Other Parts Discussed in Thread: CD4051B, MPC508
I'm designing an 8:1 standard-definition NTSC video multiplexer using 2x CD4066B. Video sources are small cameras that operate on a single 3.3 to 5V rail.
At paragraph 3 on pg 1, the CD4066B datasheet says, "...the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off)."
At paragraph 8.1 on pg 14, this idea is reinforced: "...the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off). Thus when the control of the device is low, the output of the switch goes to VSS while when the control is high the output of the device goes to VDD."
Both of these statements seem to contradict the bottom line of Table 1 on pg 14, which states that the output is high impedance when the control pin is low. The sample application circuit in Figure 16 on pg 13 suggests that Table 1 is correct, as it shows four outputs bused together, but the first two paragraphs above lead me to believe that any OFF output would pull the bus to Vss.
Which interpretation is correct? Can I bus eight outputs together, or will any OFF output short the rest to Vss?
If my video signal has a DC offset such that the entire 1V pk-pk signal is above 0V (I don't have the cameras yet, but I suspect it will be), can I simplify my design by tying Vss to 0V, and do away with the negative rail, or does the CD4066B require the negative rail for some internal purpose?
Thank you.